Lines Matching full:cycles
553 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
968 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
975 /* Wait the specified 50 PCI cycles after a reset */
1368 /* BugFixes: The 21143-TD hangs with PCI Write-and-Invalidate cycles.
