Lines Matching refs:cpu_data
25 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
28 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
31 #define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
36 #define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
39 #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
48 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
51 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
54 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
57 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
60 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
63 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
66 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
69 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
72 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
75 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
78 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
81 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
84 #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
87 #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
90 #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
93 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
96 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
99 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
102 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
118 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
125 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
128 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
131 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
134 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
146 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
150 #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
154 #define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
159 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
162 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
165 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
194 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
200 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
206 #define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
210 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz
213 #define cpu_icache_line_size() cpu_data[0].icache.linesz
216 #define cpu_scache_line_size() cpu_data[0].scache.linesz
