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134 	/* Interrupt 0x000100-0x0001FF */
225 /* PCI Interrupt Acknowledge Cycle 0x030000 */
329 #define BRIDGE_INT_STATUS 0x000104 /* Interrupt Status */
330 #define BRIDGE_INT_ENABLE 0x00010C /* Interrupt Enables */
332 #define BRIDGE_INT_MODE 0x00011C /* Interrupt Mode */
333 #define BRIDGE_INT_DEVICE 0x000124 /* Interrupt Device */
369 #define BRIDGE_PCI_IACK 0x00030000 /* PCI Interrupt Ack */
486 /* Bridge interrupt status register bits definition */
551 /* Bridge interrupt enable register bits definition */
579 /* Bridge interrupt reset register bits definition */
621 /* Bridge interrupt(x) register bits definition */
633 * interrupt(x) register.
638 * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to
687 /* Bridge interrupt mode register bits definition */