Lines Matching full:irq
26 #define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
68 #define HPC3_SBCD_XIE 0x00004000 /* Send IRQ when done with cur buf */
72 #define HPC3_SCTRL_IRQ 0x01 /* IRQ asserted, either dma done or parity */
121 #define HPC3_ERXCTRL_STAT6 0x00000040 /* Rdonly irq status */
168 #define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */
193 /* HPC3 irq status regs. Due to a peculiar bug you need to
197 * reliably report bits 9:5 of the hpc3 irq status. I told
200 volatile u32 istat0; /* Irq status, only bits <4:0> reliable. */
201 #define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */
202 #define HPC3_ISTAT_SC0MASK 0x100 /* irq bit for scsi channel 0 */
203 #define HPC3_ISTAT_SC1MASK 0x200 /* irq bit for scsi channel 1 */
216 volatile u32 istat1; /* Irq status, only bits <9:5> reliable. */
