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30 #define	PI_IO_PROTECT		0x000010 /* Interrupt Pending Protection    */
68 /* Regular Interrupt register checking. */
73 #define PI_INT_MASK0_A 0x0000a8 /* Interrupt Mask 0 for CPU A */
74 #define PI_INT_MASK1_A 0x0000b0 /* Interrupt Mask 1 for CPU A */
75 #define PI_INT_MASK0_B 0x0000b8 /* Interrupt Mask 0 for CPU B */
76 #define PI_INT_MASK1_B 0x0000c0 /* Interrupt Mask 1 for CPU B */
82 #define PI_CC_PEND_SET_A 0x0000c8 /* CC Interrupt Pending Set, CPU A */
83 #define PI_CC_PEND_SET_B 0x0000d0 /* CC Interrupt Pending Set, CPU B */
84 #define PI_CC_PEND_CLR_A 0x0000d8 /* CC Interrupt Pending Clr, CPU A */
85 #define PI_CC_PEND_CLR_B 0x0000e0 /* CC Interrupt Pending Clr, CPU B */
86 #define PI_CC_MASK 0x0000e8 /* CC Interrupt mask */
124 #define PI_GFX_INT_CNTR_A 0x000318 /* Graphics interrupt counter A */
125 #define PI_GFX_INT_CMP_A 0x000320 /* Graphics interrupt comparator A */
129 #define PI_GFX_INT_CNTR_B 0x000340 /* Graphics interrupt counter B */
130 #define PI_GFX_INT_CMP_B 0x000348 /* Graphics interrupt comparator B */
136 #define PI_ERR_INT_PEND 0x000400 /* Error Interrupt Pending */
137 #define PI_ERR_INT_MASK_A 0x000408 /* Error Interrupt mask for CPU A */
138 #define PI_ERR_INT_MASK_B 0x000410 /* Error Interrupt mask for CPU B */
374 /* Interrupt pending bits on R10000 */