Lines Matching refs:x20
24 #define TIMPANI_MREF_MREF_200K_MODE_EN_M 0x20
135 #define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_M 0x20
182 #define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_M 0x20
225 #define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_M 0x20
345 #define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_M 0x20
424 #define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_M 0x20
471 #define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_M 0x20
735 #define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_M 0x20
798 #define TIMPANI_A_CDAC_RX_CLK_CTL (0x20)
969 #define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_M 0x20
1000 #define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_M 0x20
1332 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_M 0x20
1381 #define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_M 0x20
1430 #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_M 0x20
1502 #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_46_5 0x20
1561 #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_46_5 0x20
1620 #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_46_5 0x20
1684 #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_46_5 0x20
1772 #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_M 0x20
1819 #define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_M 0x20
1865 #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_M 0x20
1911 #define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_M 0x20
1960 #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_M 0x20
2002 #define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_M 0x20
2062 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_M 0x20
2101 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_M 0x20
2565 #define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_M 0x20
2943 #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_M 0x20
2980 #define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_M 0x20
3064 #define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_M 0x20
3160 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_M 0x20
3202 #define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_M 0x20
3229 #define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_M 0x20
3260 #define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_M 0x20
3297 #define TIMPANI_CDC_CH_CTL_RX2_EN_R_M 0x20
3402 #define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_M 0x20
3447 #define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_M 0x20
3531 #define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_M 0x20
3615 #define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_M 0x20
3673 #define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_M 0x20
3908 #define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_M 0x20
4084 #define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_M 0x20
4111 #define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_M 0x20
4138 #define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_M 0x20
4261 #define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_M 0x20
4338 #define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_M 0x20
4561 #define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_M 0x20
4860 #define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_M 0x20
