Lines Matching refs:xC
522 #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_M 0xC
559 #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_M 0xC
599 #define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_M 0xC
829 xC
955 #define TIMPANI_CDAC_REF_CTL2_POR 0xc
977 #define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_M 0xC
1010 #define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_M 0xC
1211 xC
1247 #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_75UA 0xC
1266 #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_75UA 0xC
1482 #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_16_5 0xC
1541 #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_16_5 0xC
1600 #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_16_5 0xC
1664 #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_16_5 0xC
1728 #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_6_0DB 0xC
1747 #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_6_0DB 0xC
2072 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_M 0xC
2111 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_M 0xC
2151 #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_M 0xC
2286 #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_12 0xC
2313 #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3327 0xC
2332 #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3327 0xC
2460 #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_12 0xC
2488 #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3327 0xC
2507 #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3327 0xC
2529 #define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_33PER 0xC
2575 #define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_M 0xC
2613 #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_M 0xC
2836 #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_M 0xC
2990 #define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_M 0xC
3116 #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_BREAK_BEFORE_MAKE_OUT_CP 0xC
3135 #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_BREAK_BEFORE_MAKE_OUT_CN 0xC
3223 #define TIMPANI_CDC_RX1_CTL_POR 0xc
3235 #define TIMPANI_CDC_RX1_CTL_RX1_RATE_M 0xC
3254 #define TIMPANI_CDC_TX_I2S_CTL_POR 0xc
3266 #define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_M 0xC
3760 #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_M 0xC
3797 #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_M 0xC
3902 #define TIMPANI_CDC_RX2_CTL_POR 0xc
3914 #define TIMPANI_CDC_RX2_CTL_RX2_RATE_M 0xC
4039 #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_M 0xC
4887 #define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_M 0xC
