Lines Matching full:instruction
91 does not require register allocation, instruction selection, or any of the other
113 1. `Instruction Selection`_ --- This phase determines an efficient way to
114 express the input LLVM code in the target instruction set. This stage
115 produces the initial code for the program in the target instruction set, then
122 instructions produced by the instruction selection phase, determines an
125 describe this in the `instruction selection section`_ because it operates on
130 the instruction selector. Optimizations like modulo-scheduling or peephole
153 The code generator is based on the assumption that the instruction selector will
172 information (e.g., an ``add`` instruction is almost identical to a ``sub``
173 instruction). In order to allow the maximum amount of commonality to be
238 The ``TargetLowering`` class is used by SelectionDAG based instruction selectors
275 registers). Each SSA virtual register created by the instruction selector has
290 whether the instruction has certain target-independent properties (accesses
308 instructions are supported, instruction latencies and instruction execution
349 about how to interpret the instruction (i.e., what the semantics of the
350 instruction are); for that you must refer to the :raw-html:`<tt>`
353 The operands of a machine instruction can be of several different types: a
358 By convention, the LLVM code generator orders instruction operands so that all
360 are normally printed in other orders. For example, the SPARC add instruction:
367 instruction like this:
389 // instruction. The '1' specifies how many operands will be added.
400 // Create a 'cmp Reg, 0' instruction, no destination reg.
403 // Create an 'sahf' instruction which takes no operands and stores nothing.
406 // Create a self looping branch instruction.
410 specify the number of operands that the machine instruction will take. This
424 of fixed registers. In particular, there are often places in the instruction
426 in a particular register. This can occur due to limitations of the instruction
429 instruction selector should emit code that copies a virtual register into or out
441 The X86 instruction selector produces this machine code for the ``div`` and
471 instruction stream to be isolated in the instruction selector. Note that
484 considered to be clobbered by the instruction.
505 corresponds to the LLVM code input to the instruction selector, but there can be
517 corresponds one-to-one with the LLVM function input to the instruction selector.
583 inside bundles. The top level BUNDLE instruction must have the correct set of
685 The ``MCInst`` class is a target-independent representation of an instruction.
692 layer. It is the type used by the instruction encoder, the instruction printer,
708 Instruction Selection
711 Instruction Selection is the process of translating LLVM code presented to the
714 instruction selector.
716 Portions of the DAG instruction selector are generated from the target
717 description (``*.td``) files. Our goal is for the entire instruction selector
727 is amenable to instruction selection using automatic techniques
729 well-suited to other phases of code generation; in particular, instruction
776 SelectionDAG Instruction Selection Process
779 SelectionDAG-based instruction selection consists of the following steps:
802 #. `Select instructions from DAG`_ --- Finally, the target instruction selector
807 order to the instructions in the target-instruction DAG and emits them into
942 The Select phase is the bulk of the target-specific code for instruction
961 output of the instruction selector might look like this DAG:
967 The ``FMADDS`` instruction is a ternary instruction that multiplies its first
969 The ``FADDS`` instruction is a simple binary single-precision add instruction.
971 instruction definitions:
986 The highlighted portion of the instruction definitions indicates the pattern
991 The TableGen DAG instruction selector generator reads the instruction patterns
995 * At compiler-compiler time, it analyzes your instruction patterns and tells you
1025 instruction. To tell tblgen how to do this, it defines:
1033 If none of the single-instruction patterns for loading an immediate into a
1037 instruction". To make this work, the ``LO16``/``HI16`` node transformations
1041 * When using the 'Pat' class to map a pattern to an instruction that has one
1057 complex operand ``dst`` of class ``memri`` in the ``STWU`` instruction.
1069 for your instruction selector.
1084 Despite these limitations, the instruction selector generator is still quite
1085 useful for most of the binary and logical operations in typical instruction
1098 try to cover instruction latencies). Once an order is established, the DAG is
1102 Note that this phase is logically separate from the instruction selection phase,
1132 the set of registers that are immediately dead after the instruction (i.e., the
1133 instruction calculates the value, but it is never used) and the set of registers
1134 that are used by the instruction, but are never used after the instruction
1149 instruction during live intervals analysis. If the last basic block of a
1164 the basic block with the defining instruction is encountered.
1259 Before register allocation, the operands of an instruction are mostly virtual
1263 ``MachineOperand::getReg()``. An instruction may define or use a register. For
1267 instruction. The method ``MachineOperand::isDef()`` informs if that registers is
1277 registers are implicitly defined by an instruction, use the
1279 of the target instruction. One important difference between explicit and
1281 instruction, whereas the former may vary depending on the program being
1282 compiled. For example, an instruction that represents a function call will
1284 registers implicitly used by an instruction, use
1306 insert a store instruction, use ``TargetInstrInfo::storeRegToStackSlot(...)``,
1307 and to insert a load instruction, use ``TargetInstrInfo::loadRegFromStackSlot``.
1335 instructions are three address instructions. That is, each instruction is
1338 defined register is also one of the used register. For instance, an instruction
1347 situations where an instruction such as ``%a = ADD %b %c`` is converted to two
1355 Notice that, internally, the second instruction is represented as ``ADD
1357 the instruction.
1365 instruction sets do not implement PHI instructions. Thus, in order to generate
1377 Instruction folding
1380 *Instruction folding* is an optimization performed during register allocation
1389 can be safely substituted by the single instruction:
1397 folding instructions; a folded instruction can be quite different from the
1398 original instruction. See ``LiveIntervals::addIntervalsForSpills`` in
1548 #. Second, you need to implement an instruction printer for your target. The
1549 instruction printer takes an `MCInst`_ and renders it to a raw_ostream as
1561 instruction printer or the encoder.
1571 In a Very Long Instruction Word (VLIW) architecture, the compiler is responsible
1582 about whether an instruction can be added to a packet. This decision can be
1585 VLIW packetizer parses the instruction classes of a target and generates tables
1587 machine-independent API to determine if an instruction can be accommodated in a
1593 The packetizer reads instruction classes from a target's itineraries and creates
1596 inputs for the generated DFA represents the instruction being added to a
1599 occur on the addition of an instruction to an existing packet. If there is a
1602 mapping does not exist and that the instruction cannot be added to the packet.
1609 a target packetizer to add an instruction to an existing packet and to check
1610 whether an instruction can be added to a packet. See
1619 (in particular the instruction syntax and encodings), which means that a large
1623 Instruction Parsing
1631 Instruction Alias Processing
1634 Once the instruction is parsed, it enters the MatchInstructionImpl function.
1643 meets the needs of your instruction, because it will allow a more concise
1649 The first phase of alias processing is simple instruction mnemonic remapping for
1666 instruction (such as the operands) they can depend on global modes (the same
1675 the current instruction set.
1677 Instruction Aliases
1681 it provides new forms for the matcher to match along with a specific instruction
1682 to generate. An instruction alias has two parts: the string to match and the
1683 instruction to generate. For example:
1695 This shows a powerful example of the instruction aliases, matching the same
1697 the assembly. The result of instruction aliases can include operands in a
1698 different order than the destination instruction, and can use an input multiple
1711 for tied operands. The result of an instruction alias can also use immediates
1726 Instruction aliases can also have a Requires clause to make them subtarget
1729 If the back-end supports it, the instruction printer can automatically emit the
1734 Instruction Matching
2169 prefix byte on an instruction causes the instruction's memory access to go to
2201 Instruction naming
2204 An instruction name consists of the base name, a default operand size, and a a
