Lines Matching full:instruction
30 characteristics, such as a RISC instruction set and straightforward calling
50 descriptions of code generation stages: Instruction Selection, Scheduling and
65 reference. For details about the ARM instruction set, refer to the `ARM
92 * Describe the instruction set of the target. Use TableGen to generate code
104 DAG-to-DAG instruction selection. Also write code in ``XXXISelLowering.cpp``
186 methods are named ``get*Info``, and are intended to obtain the instruction set
321 same way for some instruction. Typical examples are register classes for
323 instruction to use any register in a specified register class to perform the
324 instruction in a similar manner. Register classes allocate virtual registers
487 // default value 1 means a single instruction
652 Instruction Set
664 generate much of the code for instruction definition:
666 * ``Target.td`` --- Where the ``Instruction``, ``Operand``, ``InstrInfo``, and
669 * ``TargetSelectionDAG.td`` --- Used by ``SelectionDAG`` instruction selection
678 * ``XXXInstrInfo.td`` --- Target-specific definitions of instruction templates,
679 condition codes, and instructions of an instruction set. For architecture
681 with SSE instruction, this file is ``X86InstrSSE.td``, and for Pentium with
691 which describes one instruction. An instruction descriptor defines:
699 The Instruction class (defined in ``Target.td``) is mostly used as a base for
700 more complex instruction classes.
704 class Instruction {
708 string AsmString = ""; // The .s format to print the instruction with.
709 list<dag> Pattern; // Set to the DAG pattern for this instruction.
717 target-specific instruction that is defined in ``XXXInstrInfo.td``. The
718 instruction objects should represent instructions from the architecture manual
722 A single instruction from the architecture manual is often modeled as multiple
724 describe an add instruction that takes a register or an immediate operand. An
728 You should define a class for each instruction category and define each opcode
731 bits to the bits of the instruction in which they are encoded (for the JIT).
732 Also you should specify how the instruction should be printed when the
737 instruction. Format 2 is for branch on condition codes and ``SETHI`` (set high
741 ``InstSP`` is a base class for other instruction classes. Additional base
749 ``SparcInstrInfo.td`` largely consists of operand and instruction definitions
751 description file entry, ``LDrr``, defines the Load Integer instruction for a
777 The sixth and final parameter is the pattern used to match the instruction
779 This parameter is detailed in the next section, :ref:`instruction-selector`.
781 Instruction class definitions are not overloaded for different operand types,
783 immediate value operands. For example, to perform a Load Integer instruction
784 for a Word from an immediate operand to a register, the following instruction
795 creation of templates to define several instruction classes at once (using the
797 pattern ``F3_12`` is defined to create 2 instruction classes each time
814 instructions, as seen below, it creates four instruction objects: ``XORrr``,
845 Instruction Operand Mapping
848 The code generator backend maps instruction operands to fields in the
849 instruction. Operands are assigned to unbound fields in the instruction in the
851 example, the Sparc target defines the ``XNORrr`` instruction as a ``F3_1``
852 format instruction having three operands.
861 The instruction templates in ``SparcInstrFormats.td`` show the base class for
866 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
911 fields. This results in the ``XNORrr`` instruction binding ``$dst``, ``$b``,
916 TableGen name. Setting the UseNamedOperandTable bit in an instruction's
955 Instruction Relation Mapping
959 particularly useful when you have multiple instruction formats and need to
960 switch between them after instruction selection. This entire feature is driven
962 according to the target-specific instruction set. Relation models are defined
964 and generates instruction relation maps using the specified information.
978 * ``isLoadFromStackSlot`` --- If the specified machine instruction is a direct
982 * ``isStoreToStackSlot`` --- If the specified machine instruction is a direct
997 store instruction for the specified operand(s).
1047 If a block ends with a single unconditional branch instruction, then
1060 instruction and return the penultimate branch in the ``TBB`` parameter.
1072 A block may end with a single conditional branch instruction that falls through
1124 Instruction Selector
1129 generation, instruction selection passes are performed to convert non-native
1132 instruction selection. Optionally, a pass may be defined (in
1138 TableGen generates code for instruction selection using the following target
1142 target-specific instruction set, generates ``XXXGenDAGISel.inc``, which is
1149 The implementation of an instruction selection pass must include a header that
1151 ``XXXTargetMachine.cpp``, a Pass Manager (PM) should add each instruction
1159 To describe instruction selector behavior, you should add patterns for lowering
1160 LLVM code into a ``SelectionDAG`` as the last parameter of the instruction
1195 for an instruction. In this example, ``SelectCode`` calls ``Select_ISD_STORE``
1217 instruction.
1266 so the instruction selection process knows what to do. The ``TargetLowering``
1500 :ref:`instruction-set`.) TableGen will produce an output file
1568 assembly for the instruction (using ``printInstruction``)
1590 instruction with a memory address operand, the ``printMemOperand`` method
1601 Subtarget support is used to inform the code generation process of instruction
1610 The UltraSPARC architecture combines V9 with UltraSPARC Visual Instruction Set
1647 "Enable UltraSPARC Visual Instruction Set extensions">;
1728 ``MachineBasicBlock`` calls ``emitInstruction`` to process each instruction and
1730 statements on the instruction types defined in ``XXXInstrInfo.h``. For
