Lines Matching defs:ISD
181 (TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
182 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
223 int ISD = TLI->InstructionOpcodeToISD(Opcode);
224 assert(ISD && "Invalid opcode");
233 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
243 if (!TLI->isOperationExpand(ISD, LT.second)) {
270 int ISD = TLI->InstructionOpcodeToISD(Opcode);
271 assert(ISD && "Invalid opcode");
294 if (TLI->isOperationLegalOrPromote(ISD, DstLT.second))
305 if (!TLI->isOperationExpand(ISD, DstLT.second))
329 if (!TLI->isOperationExpand(ISD, DstLT.second))
364 int ISD = TLI->InstructionOpcodeToISD(Opcode);
365 assert(ISD && "Invalid opcode");
368 if (ISD == ISD::SELECT) {
371 ISD = ISD::VSELECT;
376 if (!TLI->isOperationExpand(ISD, LT.second)) {
416 unsigned ISD = 0;
437 case Intrinsic::sqrt: ISD = ISD::FSQRT; break;
438 case Intrinsic::sin: ISD = ISD::FSIN; break;
439 case Intrinsic::cos: ISD = ISD::FCOS; break;
440 case Intrinsic::exp: ISD = ISD::FEXP; break;
441 case Intrinsic::exp2: ISD = ISD::FEXP2; break;
442 case Intrinsic::log: ISD = ISD::FLOG; break;
443 case Intrinsic::log10: ISD = ISD::FLOG10; break;
444 case Intrinsic::log2: ISD = ISD::FLOG2; break;
445 case Intrinsic::fabs: ISD = ISD::FABS; break;
446 case Intrinsic::floor: ISD = ISD::FFLOOR; break;
447 case Intrinsic::ceil: ISD = ISD::FCEIL; break;
448 case Intrinsic::trunc: ISD = ISD::FTRUNC; break;
450 ISD = ISD::FNEARBYINT; break;
451 case Intrinsic::rint: ISD = ISD::FRINT; break;
452 case Intrinsic::pow: ISD = ISD::FPOW; break;
453 case Intrinsic::fma: ISD = ISD::FMA; break;
454 case Intrinsic::fmuladd: ISD = ISD::FMA; break; // FIXME: mul + add?
463 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
473 if (!TLI->isOperationExpand(ISD, LT.second)) {
