Lines Matching refs:LiveRegs
135 LiveReg *LiveRegs;
175 // LiveRegs manipulations.
249 /// Set LiveRegs[rx] = dv, updating reference counts.
252 assert(LiveRegs && "Must enter basic block first.");
254 if (LiveRegs[rx].Value == dv)
256 if (LiveRegs[rx].Value)
257 release(LiveRegs[rx].Value);
258 LiveRegs[rx].Value = retain(dv);
264 assert(LiveRegs && "Must enter basic block first.");
265 if (!LiveRegs[rx].Value)
268 release(LiveRegs[rx].Value);
269 LiveRegs[rx].Value = 0;
275 assert(LiveRegs && "Must enter basic block first.");
276 if (DomainValue *dv = LiveRegs[rx].Value) {
285 assert(LiveRegs[rx].Value && "Not live after collapse?");
286 LiveRegs[rx].Value->addDomain(domain);
305 if (LiveRegs && dv->Refs > 1)
307 if (LiveRegs[rx].Value == dv)
331 if (LiveRegs[rx].Value == B)
336 // enterBasicBlock - Set up LiveRegs by merging predecessor live-out values.
344 // Set up LiveRegs to represent registers entering MBB.
345 if (!LiveRegs)
346 LiveRegs = new LiveReg[NumRegs];
350 LiveRegs[rx].Value = 0;
351 LiveRegs[rx].Def = -(1 << 20);
364 LiveRegs[rx].Def = -1;
382 LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, fi->second[rx].Def);
387 if (!LiveRegs[rx].Value) {
393 if (LiveRegs[rx].Value->isCollapsed()) {
395 unsigned Domain = LiveRegs[rx].Value->getFirstDomain();
403 merge(LiveRegs[rx].Value, pdv);
413 assert(LiveRegs && "Must enter basic block first.");
416 bool First = LiveOuts.insert(std::make_pair(MBB, LiveRegs)).second;
419 // LiveRegs was inserted in LiveOuts. Adjust all defs to be relative to
422 LiveRegs[i].Def -= CurInstr;
427 release(LiveRegs[i].Value);
428 delete[] LiveRegs;
430 LiveRegs = 0;
475 unsigned Clearance = CurInstr - LiveRegs[rx].Def;
476 LiveRegs[rx].Def = CurInstr;
539 if (LiveRegs)
546 if (DomainValue *dv = LiveRegs[rx].Value) {
578 const LiveReg &LR = LiveRegs[rx];
618 if (LiveRegs[*i].Value == Latest)
638 if (!LiveRegs[rx].Value || (mo.isDef() && LiveRegs[rx].Value != dv)) {
649 LiveRegs = 0;
