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Lines Matching refs:VirtRegI

135     VirtRegI = VirtReg->begin();
137     LiveUnionI.find(VirtRegI->start);
143     assert(VirtRegI != VirtRegEnd && "Reached end of VirtReg");
146     while (VirtRegI->start < LiveUnionI.stop() &&
147            VirtRegI->end > LiveUnionI.start()) {
164     // beyond VirtRegI.
165     assert(VirtRegI->end <= LiveUnionI.start() && "Expected non-overlap");
168     VirtRegI = VirtReg->advanceTo(VirtRegI, LiveUnionI.start());
169     if (VirtRegI == VirtRegEnd)
173     if (VirtRegI->start < LiveUnionI.stop())
177     LiveUnionI.advanceTo(VirtRegI->start);