Lines Matching full:getparent
62 if (Kills[i]->getParent() == MBB)
101 if (VRInfo.Kills[i]->getParent() == MBB) {
140 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
149 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
168 if (MBB == MRI->getVRegDef(reg)->getParent()) return;
179 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
617 MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
725 if (Def && Def->getParent() == &MBB)
755 if (VI.Kills[i]->getParent() == SuccMBB)
762 if (VI.Kills[i]->getParent() == SuccMBB1 ||
763 VI.Kills[i]->getParent() == SuccMBB2)
771 VI.Kills[i]->getParent()))
