Lines Matching refs:LRI
245 void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
246 addKillFlag(*LRI);
247 assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &&
249 PhysRegState[LRI->PhysReg] = regFree;
252 LiveVirtRegs.erase(LRI);
259 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
260 if (LRI != LiveVirtRegs.end())
261 killVirtReg(LRI);
269 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
270 assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
271 spillVirtReg(MI, LRI);
276 LiveRegMap::iterator LRI) {
277 LiveReg &LR = *LRI;
278 assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping");
285 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
287 const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
288 int FI = getStackSpaceFor(LRI->VirtReg, RC);
297 LiveDbgValueMap[LRI->VirtReg];
324 killVirtReg(LRI);
500 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
501 assert(LRI != LiveVirtRegs.end() && "VirtReg disappeared");
502 assignVirtToPhysReg(*LRI, PhysReg);
503 return LRI;
508 LiveRegMap::iterator LRI,
510 const unsigned VirtReg = LRI->VirtReg;
530 // That invalidates LRI, so run a new lookup for VirtReg.
541 assignVirtToPhysReg(*LRI, PhysReg);
542 return LRI;
557 assignVirtToPhysReg(*LRI, *I);
558 return LRI;
567 // That invalidates LRI, so run a new lookup for VirtReg.
583 LiveRegMap::iterator LRI;
585 tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
595 LRI = allocVirtReg(MI, LRI, Hint);
596 } else if (LRI->LastUse) {
599 if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse())
600 addKillFlag(*LRI);
602 assert(LRI->PhysReg && "Register not assigned");
603 LRI->LastUse = MI;
604 LRI->LastOpNum = OpNum;
605 LRI->Dirty = true;
606 markRegUsedInInstr(LRI->PhysReg);
607 return LRI;
616 LiveRegMap::iterator LRI;
618 tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
621 LRI = allocVirtReg(MI, LRI, Hint);
625 << PrintReg(LRI->PhysReg, TRI) << "\n");
626 TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);
628 } else if (LRI->Dirty) {
653 assert(LRI->PhysReg && "Register not assigned");
654 LRI->LastUse = MI;
655 LRI->LastOpNum = OpNum;
656 markRegUsedInInstr(LRI->PhysReg);
657 return LRI;
736 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
737 unsigned PhysReg = LRI->PhysReg;
745 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
746 PartialDefs.push_back(LRI->PhysReg);
759 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
760 unsigned PhysReg = LRI->PhysReg;
847 LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
848 if (LRI != LiveVirtRegs.end())
849 setPhysReg(MI, i, LRI->PhysReg);
964 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);
965 unsigned PhysReg = LRI->PhysReg;
968 killVirtReg(LRI);
1020 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);
1021 unsigned PhysReg = LRI->PhysReg;
