Lines Matching full:setcc
549 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
550 // that selects between the values 1 and 0, making it equivalent to a setcc.
556 if (N.getOpcode() == ISD::SETCC) {
575 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
1141 case ISD::SETCC: return visitSETCC(N);
2649 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2689 TLI.isOperationLegal(ISD::SETCC,
3164 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3201 TLI.isOperationLegal(ISD::SETCC,
3461 llvm_unreachable("Unhandled SetCC Equivalent!");
3462 case ISD::SETCC:
3471 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3482 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
4064 // %c = setcc eq %b, 0
4203 // fold selects based on a setcc into other things, such as min/max/abs
4204 if (N0.getOpcode() == ISD::SETCC) {
4231 if (N0.getOpcode() == ISD::SETCC) {
4286 if (SCC.getOpcode() == ISD::SETCC)
4324 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4325 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4373 // Extend SetCC uses if necessary.
4375 SDNode *SetCC = SetCCs[i];
4379 SDValue SOp = SetCC->getOperand(j);
4386 Ops.push_back(SetCC->getOperand(2));
4387 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4548 if (N0.getOpcode() == ISD::SETCC) {
4549 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4555 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
4556 // of the same size as the compared operands. Only optimize sext(setcc())
4582 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4593 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(VT)))) {
4624 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
4842 if (N0.getOpcode() == ISD::SETCC) {
4844 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4882 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
5030 if (N0.getOpcode() == ISD::SETCC) {
5031 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
5062 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
6481 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6482 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
6493 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
6496 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
6538 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6540 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
6807 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
6809 if (N1.getOpcode() == ISD::SETCC &&
6839 // %c = setcc eq %b, 0
6857 SDValue SetCC =
6864 MVT::Other, Chain, SetCC, N2);
6873 // Replace the uses of SRL with SETCC
6875 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6918 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
6930 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor),
6934 // Replace the uses of XOR with SETCC
6936 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6940 MVT::Other, Chain, SetCC, N2);
6959 // Use SimplifySetCC to simplify SETCC's.
6965 // fold to a simpler setcc
6966 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
9628 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
9634 // break it down into a new SETCC node, and a new SELECT node, and then return
9637 // Check to see if we got a select_cc back (to turn into setcc/select).
9640 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
9644 AddToWorkList(SETCC.getNode());
9646 SCC.getOperand(2), SCC.getOperand(3), SETCC);
9948 // Get a SetCC of the condition
9949 // NOTE: Don't create a SETCC if it's not legal on this target.
9951 TLI.isOperationLegal(ISD::SETCC,
9954 // cast from setcc result type to select result type
9976 // shl setcc result by log2 n2c
9983 // Check to see if this is the equivalent of setcc
9984 // FIXME: Turn all of these into setcc if setcc if setcc is legal
9989 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(XType))) {