Lines Matching refs:Kill
221 IntegerReg, /*Kill=*/false);
923 IntReg, /*Kill=*/true,
930 ISD::BITCAST, IntResultReg, /*Kill=*/true);
1203 MaterialReg, /*Kill=*/true);
1227 .addReg(Op0, Op0IsKill * RegState::Kill);
1230 .addReg(Op0, Op0IsKill * RegState::Kill);
1247 .addReg(Op0, Op0IsKill * RegState::Kill)
1248 .addReg(Op1, Op1IsKill * RegState::Kill);
1251 .addReg(Op0, Op0IsKill * RegState::Kill)
1252 .addReg(Op1, Op1IsKill * RegState::Kill);
1269 .addReg(Op0, Op0IsKill * RegState::Kill)
1270 .addReg(Op1, Op1IsKill * RegState::Kill)
1271 .addReg(Op2, Op2IsKill * RegState::Kill);
1274 .addReg(Op0, Op0IsKill * RegState::Kill)
1275 .addReg(Op1, Op1IsKill * RegState::Kill)
1276 .addReg(Op2, Op2IsKill * RegState::Kill);
1292 .addReg(Op0, Op0IsKill * RegState::Kill)
1296 .addReg(Op0, Op0IsKill * RegState::Kill)
1313 .addReg(Op0, Op0IsKill * RegState::Kill)
1318 .addReg(Op0, Op0IsKill * RegState::Kill)
1336 .addReg(Op0, Op0IsKill * RegState::Kill)
1340 .addReg(Op0, Op0IsKill * RegState::Kill)
1358 .addReg(Op0, Op0IsKill * RegState::Kill)
1359 .addReg(Op1, Op1IsKill * RegState::Kill)
1363 .addReg(Op0, Op0IsKill * RegState::Kill)
1364 .addReg(Op1, Op1IsKill * RegState::Kill)
1382 .addReg(Op0, Op0IsKill * RegState::Kill)
1383 .addReg(Op1, Op1IsKill * RegState::Kill)
1387 .addReg(Op0, Op0IsKill * RegState::Kill)
1388 .addReg(Op1, Op1IsKill * RegState::Kill)
