Lines Matching refs:EXTLOAD
275 // Only do this if the target has a native EXTLOAD instruction from
277 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
290 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
375 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
491 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
585 // with a "move to register" or "extload into register" instruction, then
932 // that these bits are zero. It is also useful for EXTLOAD, since it
939 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
948 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
972 assert(!SrcVT.isVector() && "Unsupported extload!");
985 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1015 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1080 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1087 case ISD::EXTLOAD:
1107 assert(ExtType != ISD::EXTLOAD &&
1108 "EXTLOAD should always be supported!");
1109 // Turn the unsupported load into an EXTLOAD followed by an explicit
1111 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1399 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1729 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
2406 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2896 // EXTLOAD pair, targeting a temporary location (a stack slot).
