Lines Matching refs:ISD
277 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
290 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
307 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
322 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
363 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
365 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
375 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
387 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
404 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
411 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
420 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
429 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
445 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
447 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
448 ISD::ANY_EXTEND, dl, VT, Result);
483 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
484 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
491 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
504 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
528 ISD::LoadExtType HiExtType = LD->getExtensionType();
531 if (HiExtType == ISD::NON_EXTLOAD)
532 HiExtType = ISD::ZEXTLOAD;
537 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
540 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
550 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
552 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
561 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
562 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
564 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
602 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
606 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
607 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
627 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
689 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
695 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
721 switch (TLI.getOperationAction(ISD::STORE, VT)) {
741 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
744 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
795 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
797 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
808 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
816 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
825 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
854 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
872 ISD::LoadExtType ExtType = LD->getExtensionType();
873 if (ExtType == ISD::NON_EXTLOAD) {
908 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
947 ISD::LoadExtType NewExtType =
948 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
957 if (ExtType == ISD::SEXTLOAD)
959 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
962 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
964 Result = DAG.getNode(ISD::AssertZext, dl,
987 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
994 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1003 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1007 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1012 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1023 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1025 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1033 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1037 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1042 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1080 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1087 case ISD::EXTLOAD:
1089 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1091 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1092 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1107 assert(ExtType != ISD::EXTLOAD &&
1111 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1116 if (ExtType == ISD::SEXTLOAD)
1117 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1141 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1153 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1160 case ISD::INTRINSIC_W_CHAIN:
1161 case ISD::INTRINSIC_WO_CHAIN:
1162 case ISD::INTRINSIC_VOID:
1163 case ISD::STACKSAVE:
1166 case ISD::VAARG:
1172 case ISD::SINT_TO_FP:
1173 case ISD::UINT_TO_FP:
1174 case ISD::EXTRACT_VECTOR_ELT:
1178 case ISD::FP_ROUND_INREG:
1179 case ISD::SIGN_EXTEND_INREG: {
1184 case ISD::ATOMIC_STORE: {
1189 case ISD::SELECT_CC:
1190 case ISD::SETCC:
1191 case ISD::BR_CC: {
1192 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1193 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1194 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1196 ISD::CondCode CCCode =
1200 if (Node->getOpcode() == ISD::SELECT_CC)
1208 case ISD::LOAD:
1209 case ISD::STORE:
1214 case ISD::CALLSEQ_START:
1215 case ISD::CALLSEQ_END:
1221 case ISD::EXTRACT_ELEMENT:
1222 case ISD::FLT_ROUNDS_:
1223 case ISD::SADDO:
1224 case ISD::SSUBO:
1225 case ISD::UADDO:
1226 case ISD::USUBO:
1227 case ISD::SMULO:
1228 case ISD::UMULO:
1229 case ISD::FPOWI:
1230 case ISD::MERGE_VALUES:
1231 case ISD::EH_RETURN:
1232 case ISD::FRAME_TO_ARGS_OFFSET:
1233 case ISD::EH_SJLJ_SETJMP:
1234 case ISD::EH_SJLJ_LONGJMP:
1241 case ISD::INIT_TRAMPOLINE:
1242 case ISD::ADJUST_TRAMPOLINE:
1243 case ISD::FRAMEADDR:
1244 case ISD::RETURNADDR:
1251 case ISD::DEBUGTRAP:
1254 // replace ISD::DEBUGTRAP with ISD::TRAP
1256 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1265 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1277 case ISD::SHL:
1278 case ISD::SRL:
1279 case ISD::SRA:
1280 case ISD::ROTL:
1281 case ISD::ROTR:
1294 case ISD::SRL_PARTS:
1295 case ISD::SRA_PARTS:
1296 case ISD::SHL_PARTS:
1362 case ISD::CALLSEQ_START:
1363 case ISD::CALLSEQ_END:
1365 case ISD::LOAD: {
1368 case ISD::STORE: {
1386 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1390 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1392 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1394 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1399 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1429 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1433 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1435 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1437 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1467 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1472 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1490 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1512 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1533 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1543 SignBit = DAG.getNode(ISD
1551 ISD::SETLT);
1553 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1557 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1584 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1586 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1605 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1612 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1613 ISD::CondCode InvCC = ISD::SETCC_INVALID;
1617 case ISD::SETO:
1618 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1621 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1622 case ISD::SETUO:
1623 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1626 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1627 case ISD::SETOEQ:
1628 case ISD::SETOGT:
1629 case ISD::SETOGE:
1630 case ISD::SETOLT:
1631 case ISD::SETOLE:
1632 case ISD::SETONE:
1633 case ISD::SETUEQ:
1634 case ISD::SETUNE:
1635 case ISD::SETUGT:
1636 case ISD::SETUGE:
1637 case ISD::SETULT:
1638 case ISD::SETULE:
1643 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1644 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1645 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1649 case ISD::SETLE:
1650 case ISD::SETGT:
1651 case ISD::SETGE:
1652 case ISD::SETLT:
1653 case ISD::SETNE:
1654 case ISD::SETEQ:
1655 InvCC = ISD::getSetCCSwappedOperands(CCCode);
1668 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1729 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1770 if (V.getOpcode() == ISD::UNDEF)
1791 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1813 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1830 if (V.getOpcode() == ISD::UNDEF)
1836 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1839 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2021 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2024 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2026 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2049 bool isSigned = Opcode == ISD::SDIVREM;
2137 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2138 ? ISD::FCOS : ISD::FSIN;
2147 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2238 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2248 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2271 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2279 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2282 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2303 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2305 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2306 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2307 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2308 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2309 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2311 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2320 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2324 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2326 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2327 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2329 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2330 ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2337 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2343 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2345 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2347 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2350 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2354 ISD::SETUGE);
2358 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2360 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2361 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2364 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2365 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2366 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2367 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2368 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2372 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2376 ISD::SETLT);
2398 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2406 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2415 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2438 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2439 OpToUse = ISD::SINT_TO_FP;
2445 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2446 OpToUse = ISD::UINT_TO_FP;
2456 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2479 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2480 OpToUse = ISD::FP_TO_SINT;
2484 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2485 OpToUse = ISD::FP_TO_UINT;
2498 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2510 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2511 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2512 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2514 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2515 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2516 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2517 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2518 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2519 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2520 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2521 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2522 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2524 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2525 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2526 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2527 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2528 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2529 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2530 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2531 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2532 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2533 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2534 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2535 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2536 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2537 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2538 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2539 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2540 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2541 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2542 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2543 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2544 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2554 case ISD::CTPOP: {
2571 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2572 DAG.getNode(ISD::AND, dl, VT,
2573 DAG.getNode(ISD::SRL, dl, VT, Op,
2577 Op = DAG.getNode(ISD::ADD, dl, VT,
2578 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2579 DAG.getNode(ISD::AND, dl, VT,
2580 DAG.getNode(ISD::SRL, dl, VT, Op,
2584 Op = DAG.getNode(ISD::AND, dl, VT,
2585 DAG.getNode(ISD::ADD, dl, VT, Op,
2586 DAG.getNode(ISD::SRL, dl, VT, Op,
2590 Op = DAG.getNode(ISD::SRL, dl, VT,
2591 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2596 case ISD::CTLZ_ZERO_UNDEF:
2598 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2599 case ISD::CTLZ: {
2614 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2615 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2618 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2620 case ISD::CTTZ_ZERO_UNDEF:
2622 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2623 case ISD::CTTZ: {
2629 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2631 DAG.getNode(ISD::SUB, dl, VT, Op,
2633 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2634 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2635 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2636 return DAG.getNode(ISD::SUB, dl, VT,
2638 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2639 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2652 case ISD::ATOMIC_SWAP:
2661 case ISD::ATOMIC_CMP_SWAP:
2670 case ISD::ATOMIC_LOAD_ADD:
2679 case ISD::ATOMIC_LOAD_SUB:
2688 case ISD::ATOMIC_LOAD_AND:
2697 case ISD::ATOMIC_LOAD_OR:
2706 case ISD::ATOMIC_LOAD_XOR:
2715 case ISD::ATOMIC_LOAD_NAND:
2734 case ISD::CTPOP:
2735 case ISD::CTLZ:
2736 case ISD::CTLZ_ZERO_UNDEF:
2737 case ISD::CTTZ:
2738 case ISD::CTTZ_ZERO_UNDEF:
2742 case ISD::BSWAP:
2745 case ISD::FRAMEADDR:
2746 case ISD::RETURNADDR:
2747 case ISD::FRAME_TO_ARGS_OFFSET:
2750 case ISD::FLT_ROUNDS_:
2753 case ISD::EH_RETURN:
2754 case ISD::EH_LABEL:
2755 case ISD::PREFETCH:
2756 case ISD::VAEND:
2757 case ISD::EH_SJLJ_LONGJMP:
2762 case ISD::EH_SJLJ_SETJMP:
2768 case ISD::ATOMIC_FENCE: {
2786 case ISD::ATOMIC_LOAD: {
2789 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2800 case ISD::ATOMIC_STORE: {
2802 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2815 case ISD::ATOMIC_SWAP:
2816 case ISD::ATOMIC_LOAD_ADD:
2817 case ISD::ATOMIC_LOAD_SUB:
2818 case ISD::ATOMIC_LOAD_AND:
2819 case ISD::ATOMIC_LOAD_OR:
2820 case ISD::ATOMIC_LOAD_XOR:
2821 case ISD::ATOMIC_LOAD_NAND:
2822 case ISD::ATOMIC_LOAD_MIN:
2823 case ISD::ATOMIC_LOAD_MAX:
2824 case ISD::ATOMIC_LOAD_UMIN:
2825 case ISD::ATOMIC_LOAD_UMAX:
2826 case ISD::ATOMIC_CMP_SWAP: {
2832 case ISD::DYNAMIC_STACKALLOC:
2835 case ISD::MERGE_VALUES:
2839 case ISD::UNDEF: {
2849 case ISD::TRAP: {
2865 case ISD::FP_ROUND:
2866 case ISD::BITCAST:
2871 case ISD::FP_EXTEND:
2877 case ISD::SIGN_EXTEND_INREG: {
2888 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2890 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2894 case ISD::FP_ROUND_INREG: {
2907 case ISD::SINT_TO_FP:
2908 case ISD::UINT_TO_FP:
2909 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2913 case ISD::FP_TO_UINT: {
2924 Tmp1, ISD::SETLT);
2925 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2926 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2927 DAG.getNode(ISD::FSUB, dl, VT,
2929 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2935 case ISD::VAARG: {
2950 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2954 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2960 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2973 case ISD::VACOPY: {
2986 case ISD::EXTRACT_VECTOR_ELT:
2989 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2995 case ISD::EXTRACT_SUBVECTOR:
2998 case ISD::INSERT_SUBVECTOR:
3001 case ISD::CONCAT_VECTORS: {
3005 case ISD::SCALAR_TO_VECTOR:
3008 case ISD::INSERT_VECTOR_ELT:
3013 case ISD::VECTOR_SHUFFLE: {
3039 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3040 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3072 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3076 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3082 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3084 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3088 case ISD::EXTRACT_ELEMENT: {
3092 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3095 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3098 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3104 case ISD::STACKSAVE:
3116 case ISD::STACKRESTORE:
3126 case ISD::FCOPYSIGN:
3129 case ISD::FNEG:
3132 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3136 case ISD::FABS: {
3142 Tmp1, Tmp2, ISD::SETUGT);
3143 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3148 case ISD::FSQRT:
3153 case ISD::FSIN:
3154 case ISD::FCOS: {
3156 bool isSIN = Node->getOpcode() == ISD::FSIN;
3157 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3159 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3163 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3178 case ISD::FSINCOS:
3182 case ISD::FLOG:
3187 case ISD::FLOG2:
3192 case ISD::FLOG10:
3197 case ISD::FEXP:
3202 case ISD::FEXP2:
3207 case ISD::FTRUNC:
3212 case ISD::FFLOOR:
3217 case ISD::FCEIL:
3222 case ISD::FRINT:
3227 case ISD::FNEARBYINT:
3234 case ISD::FPOWI:
3239 case ISD::FPOW:
3244 case ISD::FDIV:
3249 case ISD::FREM:
3254 case ISD::FMA:
3259 case ISD::FP16_TO_FP32:
3262 case ISD::FP32_TO_FP16:
3265 case ISD::ConstantFP: {
3273 case ISD::FSUB: {
3275 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3276 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3278 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3279 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3283 case ISD::SUB: {
3285 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3286 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3288 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3290 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3291 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3294 case ISD::UREM:
3295 case ISD::SREM: {
3297 bool isSigned = Node->getOpcode() == ISD::SREM;
3298 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3299 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3312 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3313 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3327 case ISD::UDIV:
3328 case ISD::SDIV: {
3329 bool isSigned = Node->getOpcode() == ISD::SDIV;
3330 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3351 case ISD::MULHU:
3352 case ISD::MULHS: {
3353 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3354 ISD::SMUL_LOHI;
3364 case ISD::SDIVREM:
3365 case ISD::UDIVREM:
3369 case ISD::MUL: {
3377 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3378 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3379 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3380 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3383 OpToUse = ISD::SMUL_LOHI;
3385 OpToUse = ISD::UMUL_LOHI;
3387 OpToUse = ISD::SMUL_LOHI;
3389 OpToUse = ISD::UMUL_LOHI;
3403 case ISD::SADDO:
3404 case ISD::SSUBO: {
3407 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3408 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3424 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3425 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3427 Node->getOpcode() == ISD::SADDO ?
3428 ISD::SETEQ : ISD::SETNE);
3430 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3431 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3433 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3437 case ISD::UADDO:
3438 case ISD::USUBO: {
3441 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3442 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3446 Node->getOpcode () == ISD::UADDO ?
3447 ISD::SETULT : ISD::SETUGT));
3450 case ISD::UMULO:
3451 case ISD::SMULO: {
3459 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3460 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3461 bool isSigned = Node->getOpcode() == ISD::SMULO;
3463 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3473 ISD::MUL, dl, WideVT, LHS, RHS);
3474 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3476 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3497 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3499 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3508 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3510 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3521 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3523 ISD::SETNE);
3526 DAG.getConstant(0, VT), ISD::SETNE);
3532 case ISD::BUILD_PAIR: {
3534 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3535 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3536 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3539 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3542 case ISD::SELECT:
3546 if (Tmp1.getOpcode() == ISD::SETCC) {
3553 Tmp2, Tmp3, ISD::SETNE);
3557 case ISD::BR_JT: {
3568 Index = DAG.getNode(ISD::MUL, dl, PTy,
3570 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3573 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3581 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3584 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3588 case ISD::BRCOND:
3593 if (Tmp2.getOpcode() == ISD::SETCC) {
3594 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3600 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3601 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3603 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3604 DAG.getCondCode(ISD::SETNE), Tmp3,
3610 case ISD::SETCC: {
3635 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3641 case ISD::SELECT_CC: {
3653 CC = DAG.getCondCode(ISD::SETNE);
3654 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3659 case ISD::BR_CC: {
3670 Tmp4 = DAG.getCondCode(ISD::SETNE);
3671 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3676 case ISD::BUILD_VECTOR:
3679 case ISD::SRA:
3680 case ISD::SRL:
3681 case ISD::SHL: {
3690 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3694 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3702 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3707 case ISD::GLOBAL_OFFSET_TABLE:
3708 case ISD::GlobalAddress:
3709 case ISD::GlobalTLSAddress:
3710 case ISD::ExternalSymbol:
3711 case ISD::ConstantPool:
3712 case ISD::JumpTable:
3713 case ISD::INTRINSIC_W_CHAIN:
3714 case ISD::INTRINSIC_WO_CHAIN:
3715 case ISD::INTRINSIC_VOID:
3728 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3729 Node->getOpcode() == ISD::SINT_TO_FP ||
3730 Node->getOpcode() == ISD::SETCC) {
3737 case ISD::CTTZ:
3738 case ISD::CTTZ_ZERO_UNDEF:
3739 case ISD::CTLZ:
3740 case ISD::CTLZ_ZERO_UNDEF:
3741 case ISD::CTPOP:
3743 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3747 if (Node->getOpcode() == ISD::CTTZ) {
3751 ISD::SETEQ);
3754 } else if (Node->getOpcode() == ISD::CTLZ ||
3755 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
3757 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3761 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3763 case ISD::BSWAP: {
3765 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3766 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3767 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3772 case ISD::FP_TO_UINT:
3773 case ISD::FP_TO_SINT:
3775 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3778 case ISD::UINT_TO_FP:
3779 case ISD::SINT_TO_FP:
3781 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3784 case ISD::VAARG: {
3790 TruncOp = ISD::BITCAST;
3794 TruncOp = ISD::TRUNCATE;
3811 case ISD::AND:
3812 case ISD::OR:
3813 case ISD::XOR: {
3816 ExtOp = ISD::BITCAST;
3817 TruncOp = ISD::BITCAST;
3820 ExtOp = ISD::ANY_EXTEND;
3821 TruncOp = ISD::TRUNCATE;
3831 case ISD::SELECT: {
3834 ExtOp = ISD::BITCAST;
3835 TruncOp = ISD::BITCAST;
3837 ExtOp = ISD::ANY_EXTEND;
3838 TruncOp = ISD::TRUNCATE;
3840 ExtOp = ISD::FP_EXTEND;
3841 TruncOp = ISD::FP_ROUND;
3849 if (TruncOp != ISD::FP_ROUND)
3857 case ISD::VECTOR_SHUFFLE: {
3861 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3862 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3866 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3870 case ISD::SETCC: {
3871 unsigned ExtOp = ISD::FP_EXTEND;
3873 ISD::CondCode CCCode =
3875 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3879 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3883 case ISD::FDIV:
3884 case ISD::FREM:
3885 case ISD::FPOW: {
3886 ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3887 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
3889 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3893 case ISD::FLOG2:
3894 case ISD::FEXP2:
3895 case ISD::FLOG:
3896 case ISD::FEXP: {
3897 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3899 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
