Lines Matching refs:ISD
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
154 if (Op.getOpcode() == ISD::LOAD) {
156 ISD::LoadExtType ExtType = LD->getExtensionType();
157 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
163 } else if (Op.getOpcode() == ISD::STORE) {
193 case ISD::ADD:
194 case ISD::SUB:
195 case ISD::MUL:
196 case ISD::SDIV:
197 case ISD::UDIV:
198 case ISD::SREM:
199 case ISD::UREM:
200 case ISD::FADD:
201 case ISD::FSUB:
202 case ISD::FMUL:
203 case ISD::FDIV:
204 case ISD::FREM:
205 case ISD::AND:
206 case ISD::OR:
207 case ISD::XOR:
208 case ISD::SHL:
209 case ISD::SRA:
210 case ISD::SRL:
211 case ISD::ROTL:
212 case ISD::ROTR:
213 case ISD::CTLZ:
214 case ISD::CTTZ:
215 case ISD::CTLZ_ZERO_UNDEF:
216 case ISD::CTTZ_ZERO_UNDEF:
217 case ISD::CTPOP:
218 case ISD::SELECT:
219 case ISD::VSELECT:
220 case ISD::SELECT_CC:
221 case ISD::SETCC:
222 case ISD::ZERO_EXTEND:
223 case ISD::ANY_EXTEND:
224 case ISD::TRUNCATE:
225 case ISD::SIGN_EXTEND:
226 case ISD::FP_TO_SINT:
227 case ISD::FP_TO_UINT:
228 case ISD::FNEG:
229 case ISD::FABS:
230 case ISD::FSQRT:
231 case ISD::FSIN:
232 case ISD::FCOS:
233 case ISD::FPOWI:
234 case ISD::FPOW:
235 case ISD::FLOG:
236 case ISD::FLOG2:
237 case ISD::FLOG10:
238 case ISD::FEXP:
239 case ISD::FEXP2:
240 case ISD::FCEIL:
241 case ISD::FTRUNC:
242 case ISD::FRINT:
243 case ISD::FNEARBYINT:
244 case ISD::FFLOOR:
245 case ISD::FP_ROUND:
246 case ISD::FP_EXTEND:
247 case ISD::FMA:
248 case ISD::SIGN_EXTEND_INREG:
251 case ISD::FP_ROUND_INREG:
254 case ISD::SINT_TO_FP:
255 case ISD::UINT_TO_FP:
268 case ISD::SINT_TO_FP:
269 case ISD::UINT_TO_FP:
286 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG)
288 else if (Node->getOpcode() == ISD::VSELECT)
290 else if (Node->getOpcode() == ISD::SELECT)
292 else if (Node->getOpcode() == ISD::UINT_TO_FP)
294 else if (Node->getOpcode() == ISD::FNEG)
296 else if (Node->getOpcode() == ISD::SETCC)
317 // in a different type. For example, x86 promotes ISD::AND on v2i32 to
328 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
335 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
363 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
364 ISD::SIGN_EXTEND;
383 ISD::LoadExtType ExtType = LD->getExtensionType();
426 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
434 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
454 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
455 ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
465 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
466 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
471 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
475 case ISD::EXTLOAD:
478 case ISD::ZEXTLOAD:
481 case ISD::SEXTLOAD:
484 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
485 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
502 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
510 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
512 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
553 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
561 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
566 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
593 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
594 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
595 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
596 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
614 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, &Ops[0], Ops.size());
619 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
620 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
624 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
626 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
627 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
628 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
629 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
636 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
637 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
648 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
649 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
670 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
671 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
672 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
686 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
687 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
691 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
693 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
694 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
695 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
696 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
704 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
705 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
725 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
726 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
730 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
731 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
732 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
735 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
740 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
742 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
757 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
759 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
761 Ops[i] = DAG.getNode(ISD::SETCC, dl,
769 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
