Lines Matching refs:ISD
92 // ISD Namespace
97 bool ISD::isBuildVectorAllOnes(const SDNode *N) {
99 if (N->getOpcode() == ISD::BITCAST)
102 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
107 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
137 N->getOperand(i).getOpcode() != ISD::UNDEF)
145 bool ISD::isBuildVectorAllZeros(const SDNode *N) {
147 if (N->getOpcode() == ISD::BITCAST)
150 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
155 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
177 N->getOperand(i).getOpcode() != ISD::UNDEF)
183 /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
185 bool ISD::isScalarToVector(const SDNode *N) {
186 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR)
189 if (N->getOpcode() != ISD::BUILD_VECTOR)
191 if (N->getOperand(0).getOpcode() == ISD::UNDEF)
198 if (V.getOpcode() != ISD::UNDEF)
205 /// and all operands of the specified node are ISD::UNDEF.
206 bool ISD::allOperandsUndef(const SDNode *N) {
214 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
222 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
227 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits
234 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) {
241 if (Operation > ISD::SETTRUE2)
244 return ISD::CondCode(Operation);
251 static int isSignedOp(ISD::CondCode Opcode) {
254 case ISD::SETEQ:
255 case ISD::SETNE: return 0;
256 case ISD::SETLT:
257 case ISD::SETLE:
258 case ISD::SETGT:
259 case ISD::SETGE: return 1;
260 case ISD::SETULT:
261 case ISD::SETULE:
262 case ISD::SETUGT:
263 case ISD::SETUGE: return 2;
271 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
275 return ISD::SETCC_INVALID;
281 if (Op > ISD::SETTRUE2)
285 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT
286 Op = ISD::SETNE;
288 return ISD::CondCode(Op);
295 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
299 return ISD::SETCC_INVALID;
302 ISD::CondCode Result = ISD::CondCode(Op1 & Op2);
308 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT
309 case ISD::SETOEQ: // SETEQ & SETU[LG]E
310 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE
311 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE
312 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE
367 case ISD::TargetExternalSymbol:
368 case ISD::ExternalSymbol:
371 case ISD::TargetConstant:
372 case ISD::Constant:
375 case ISD::TargetConstantFP:
376 case ISD::ConstantFP: {
380 case ISD::TargetGlobalAddress:
381 case ISD::GlobalAddress:
382 case ISD::TargetGlobalTLSAddress:
383 case ISD::GlobalTLSAddress: {
391 case ISD::BasicBlock:
394 case ISD::Register:
397 case ISD::RegisterMask:
400 case ISD::SRCVALUE:
403 case ISD::FrameIndex:
404 case ISD::TargetFrameIndex:
407 case ISD::JumpTable:
408 case ISD::TargetJumpTable:
412 case ISD::ConstantPool:
413 case ISD::TargetConstantPool: {
424 case ISD::TargetIndex: {
431 case ISD::LOAD: {
438 case ISD::STORE: {
445 case ISD::ATOMIC_CMP_SWAP:
446 case ISD::ATOMIC_SWAP:
447 case ISD::ATOMIC_LOAD_ADD:
448 case ISD::ATOMIC_LOAD_SUB:
449 case ISD::ATOMIC_LOAD_AND:
450 case ISD::ATOMIC_LOAD_OR:
451 case ISD::ATOMIC_LOAD_XOR:
452 case ISD::ATOMIC_LOAD_NAND:
453 case ISD::ATOMIC_LOAD_MIN:
454 case ISD::ATOMIC_LOAD_MAX:
455 case ISD::ATOMIC_LOAD_UMIN:
456 case ISD::ATOMIC_LOAD_UMAX:
457 case ISD::ATOMIC_LOAD:
458 case ISD::ATOMIC_STORE: {
465 case ISD::PREFETCH: {
470 case ISD::VECTOR_SHUFFLE: {
477 case ISD::TargetBlockAddress:
478 case ISD::BlockAddress: {
510 encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, bool isVolatile,
534 case ISD::HANDLENODE:
535 case ISD::EH_LABEL:
634 N->NodeType = ISD::DELETED_NODE;
651 case ISD::HANDLENODE: return false; // noop.
652 case ISD::CONDCODE:
658 case ISD::ExternalSymbol:
661 case ISD::TargetExternalSymbol: {
668 case ISD::VALUETYPE: {
680 assert(N->getOpcode() != ISD::DELETED_NODE && "DELETED_NODE in CSEMap!");
681 assert(N->getOpcode() != ISD::EntryToken && "EntryToken in CSEMap!");
788 case ISD::BUILD_PAIR: {
802 case ISD::BUILD_VECTOR: {
873 EntryNode(ISD::EntryToken, 0, DebugLoc(), getVTList(MVT::Other)),
919 getNode(ISD::ANY_EXTEND, DL, VT, Op) :
920 getNode(ISD::TRUNCATE, DL, VT, Op);
925 getNode(ISD::SIGN_EXTEND, DL, VT, Op) :
926 getNode(ISD::TRUNCATE, DL, VT, Op);
931 getNode(ISD::ZERO_EXTEND, DL, VT, Op) :
932 getNode(ISD::TRUNCATE, DL, VT, Op);
943 return getNode(ISD::AND, DL, Op.getValueType(), Op,
953 return getNode(ISD::XOR, DL, VT, Val, NegOne);
989 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
1009 Result = getNode(ISD::BUILD_VECTOR, SDLoc(), VT, &Ops[0], Ops.size());
1031 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP;
1052 Result = getNode(ISD::BUILD_VECTOR, SDLoc(), VT, &Ops[0], Ops.size());
1095 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress;
1097 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress;
1118 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex;
1136 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable;
1161 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1189 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1210 AddNodeIDNode(ID, ISD::TargetIndex, getVTList(VT), 0, 0);
1227 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
1272 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
1308 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF)
1328 if (N1.getOpcode() == ISD::UNDEF)
1334 bool N2Undef = N2.getOpcode() == ISD::UNDEF;
1368 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2);
1392 ISD::CvtCode Code) {
1396 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF))
1401 AddNodeIDNode(ID, ISD::CONVERT_RNDSAT, getVTList(VT), &Ops[0], 5);
1415 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0);
1429 AddNodeIDNode(ID, ISD::RegisterMask, getVTList(MVT::Untyped), 0, 0);
1444 AddNodeIDNode(ID, ISD::EH_LABEL, getVTList(MVT::Other), &Ops[0], 1);
1461 unsigned Opc = isTarget ? ISD::TargetBlockAddress : ISD::BlockAddress;
1484 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0);
1500 AddNodeIDNode(ID, ISD::MDNODE_SDNODE, getVTList(MVT::Other), 0, 0);
1521 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1557 SDValue N2, ISD::CondCode Cond, SDLoc dl) {
1561 case ISD::SETFALSE:
1562 case ISD::SETFALSE2: return getConstant(0, VT);
1563 case ISD::SETTRUE:
1564 case ISD::SETTRUE2: return getConstant(1, VT);
1566 case ISD::SETOEQ:
1567 case ISD::SETOGT:
1568 case ISD::SETOGE:
1569 case ISD::SETOLT:
1570 case ISD::SETOLE:
1571 case ISD::SETONE:
1572 case ISD::SETO:
1573 case ISD::SETUO:
1574 case ISD::SETUEQ:
1575 case ISD::SETUNE:
1587 case ISD::SETEQ: return getConstant(C1 == C2, VT);
1588 case ISD::SETNE: return getConstant(C1 != C2, VT);
1589 case ISD::SETULT: return getConstant(C1.ult(C2), VT);
1590 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT);
1591 case ISD::SETULE: return getConstant(C1.ule(C2), VT);
1592 case ISD::SETUGE: return getConstant(C1.uge(C2), VT);
1593 case ISD::SETLT: return getConstant(C1.slt(C2), VT);
1594 case ISD::SETGT: return getConstant(C1.sgt(C2), VT);
1595 case ISD::SETLE: return getConstant(C1.sle(C2), VT);
1596 case ISD::SETGE: return getConstant(C1.sge(C2), VT);
1605 case ISD::SETEQ: if (R==APFloat::cmpUnordered)
1608 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT);
1609 case ISD::SETNE: if (R==APFloat::cmpUnordered)
1612 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan ||
1614 case ISD::SETLT: if (R==APFloat::cmpUnordered)
1617 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT);
1618 case ISD::SETGT: if (R==APFloat::cmpUnordered)
1621 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT);
1622 case ISD::SETLE: if (R==APFloat::cmpUnordered)
1625 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan ||
1627 case ISD::SETGE: if (R==APFloat::cmpUnordered)
1630 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan ||
1632 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT);
1633 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT);
1634 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered ||
1636 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT);
1637 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered ||
1639 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan ||
1641 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT);
1642 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT);
1646 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond));
1692 case ISD::Constant:
1697 case ISD::AND:
1709 case ISD::OR:
1720 case ISD::XOR: {
1733 case ISD::MUL: {
1756 case ISD::UDIV: {
1774 case ISD::SELECT:
1784 case ISD::SELECT_CC:
1794 case ISD::SADDO:
1795 case ISD::UADDO:
1796 case ISD::SSUBO:
1797 case ISD::USUBO:
1798 case ISD::SMULO:
1799 case ISD::UMULO:
1803 case ISD::SETCC:
1809 case ISD::SHL:
1826 case ISD::SRL:
1844 case ISD::SRA:
1872 case ISD::SIGN_EXTEND_INREG: {
1908 case ISD::CTTZ:
1909 case ISD::CTTZ_ZERO_UNDEF:
1910 case ISD::CTLZ:
1911 case ISD::CTLZ_ZERO_UNDEF:
1912 case ISD::CTPOP: {
1918 case ISD::LOAD: {
1921 if (ISD::isZEXTLoad(Op.getNode()) && Op.getResNo() == 0) {
1930 case ISD::ZERO_EXTEND: {
1942 case ISD::SIGN_EXTEND: {
1968 case ISD::ANY_EXTEND: {
1978 case ISD::TRUNCATE: {
1989 case ISD::AssertZext: {
1997 case ISD::FGETSIGN:
2002 case ISD::SUB: {
2025 case ISD::ADD:
2026 case ISD::ADDE: {
2039 if (Op.getOpcode() == ISD::ADD) {
2052 case ISD::SREM:
2077 case ISD::UREM: {
2100 case ISD::FrameIndex:
2101 case ISD::TargetFrameIndex:
2110 if (Op.getOpcode() < ISD::BUILTIN_OP_END)
2113 case ISD::INTRINSIC_WO_CHAIN:
2114 case ISD::INTRINSIC_W_CHAIN:
2115 case ISD::INTRINSIC_VOID:
2140 case ISD::AssertSext:
2143 case ISD::AssertZext:
2147 case ISD::Constant: {
2152 case ISD::SIGN_EXTEND:
2156 case ISD::SIGN_EXTEND_INREG:
2165 case ISD::SRA:
2173 case ISD::SHL:
2182 case ISD::AND:
2183 case ISD::OR:
2184 case ISD::XOR: // NOT is handled here.
2196 case ISD::SELECT:
2202 case ISD::SADDO:
2203 case ISD::UADDO:
2204 case ISD::SSUBO:
2205 case ISD::USUBO:
2206 case ISD::SMULO:
2207 case ISD::UMULO:
2211 case ISD::SETCC:
2217 case ISD::ROTL:
2218 case ISD::ROTR:
2223 if (Op.getOpcode() == ISD::ROTR)
2232 case ISD::ADD:
2259 case ISD::SUB:
2286 case ISD::TRUNCATE:
2299 case ISD::SEXTLOAD: // '17' bits known
2302 case ISD::ZEXTLOAD: // '16' bits known
2310 if (Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2311 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2312 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2313 Op.getOpcode() == ISD::INTRINSIC_VOID) {
2343 /// ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an
2344 /// ISD::OR with a ConstantSDNode that is guaranteed to have the same
2348 if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) ||
2352 if (Op.getOpcode() == ISD::OR &&
2383 case ISD::OR:
2431 case ISD::SIGN_EXTEND:
2433 case ISD::ANY_EXTEND:
2434 case ISD::ZERO_EXTEND:
2435 case ISD::TRUNCATE:
2437 case ISD::UINT_TO_FP:
2438 case ISD::SINT_TO_FP: {
2442 Opcode==ISD::SINT_TO_FP,
2446 case ISD::BITCAST:
2452 case ISD::BSWAP:
2454 case ISD::CTPOP:
2456 case ISD::CTLZ:
2457 case ISD::CTLZ_ZERO_UNDEF:
2459 case ISD::CTTZ:
2460 case ISD::CTTZ_ZERO_UNDEF:
2469 case ISD::FNEG:
2472 case ISD::FABS:
2475 case ISD::FCEIL: {
2481 case ISD::FTRUNC: {
2487 case ISD::FFLOOR: {
2493 case ISD::FP_EXTEND: {
2501 case ISD::FP_TO_SINT:
2502 case ISD::FP_TO_UINT: {
2508 Opcode==ISD::FP_TO_SINT,
2515 case ISD::BITCAST:
2526 case ISD::TokenFactor:
2527 case ISD::MERGE_VALUES:
2528 case ISD::CONCAT_VECTORS:
2530 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node");
2531 case ISD::FP_EXTEND:
2539 if (Operand.getOpcode() == ISD::UNDEF)
2542 case ISD::SIGN_EXTEND:
2552 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
2554 else if (OpOpcode == ISD::UNDEF)
2558 case ISD::ZERO_EXTEND:
2568 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
2569 return getNode(ISD::ZERO_EXTEND, DL, VT,
2571 else if (OpOpcode == ISD::UNDEF)
2575 case ISD::ANY_EXTEND:
2586 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
2587 OpOpcode == ISD::ANY_EXTEND)
2590 else if (OpOpcode == ISD::UNDEF)
2594 if (OpOpcode == ISD::TRUNCATE) {
2600 case ISD::TRUNCATE:
2610 if (OpOpcode == ISD::TRUNCATE)
2611 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
2612 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
2613 OpOpcode == ISD::ANY_EXTEND) {
2619 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
2622 if (OpOpcode == ISD::UNDEF)
2625 case ISD::BITCAST:
2630 if (OpOpcode == ISD::BITCAST) // bitconv(bitconv(x)) -> bitconv(x)
2631 return getNode(ISD::BITCAST, DL, VT, Operand.getOperand(0));
2632 if (OpOpcode == ISD::UNDEF)
2635 case ISD::SCALAR_TO_VECTOR:
2642 if (OpOpcode == ISD::UNDEF)
2645 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
2651 case ISD::FNEG:
2653 if (getTarget().Options.UnsafeFPMath && OpOpcode == ISD::FSUB)
2654 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1),
2656 if (OpOpcode == ISD::FNEG) // --X -> X
2659 case ISD::FABS:
2660 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X)
2661 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0));
2730 case ISD::ADD:
2733 case ISD::SUB:
2736 case ISD::MUL:
2739 case ISD::UDIV:
2744 case ISD::UREM:
2749 case ISD::SDIV:
2754 case ISD::SREM:
2759 case ISD::AND:
2762 case ISD::OR:
2765 case ISD::XOR:
2768 case ISD::SHL:
2771 case ISD::SRL:
2774 case ISD::SRA:
2777 case ISD::ROTL:
2780 case ISD::ROTR:
2793 return getNode(ISD::BUILD_VECTOR, SDLoc(), VT, Outputs.data(),
2803 case ISD::TokenFactor:
2807 if (N1.getOpcode() == ISD::EntryToken) return N2;
2808 if (N2.getOpcode() == ISD::EntryToken) return N1;
2811 case ISD::CONCAT_VECTORS:
2813 if (N1.getOpcode() == ISD::UNDEF &&
2814 N2.getOpcode() == ISD::UNDEF)
2819 if (N1.getOpcode() == ISD::BUILD_VECTOR &&
2820 N2.getOpcode() == ISD::BUILD_VECTOR) {
2824 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
2827 case ISD::AND:
2838 case ISD::OR:
2839 case ISD::XOR:
2840 case ISD::ADD:
2841 case ISD::SUB:
2850 case ISD::UDIV:
2851 case ISD::UREM:
2852 case ISD::MULHU:
2853 case ISD::MULHS:
2854 case ISD::MUL:
2855 case ISD::SDIV:
2856 case ISD::SREM:
2861 case ISD::FADD:
2862 case ISD::FSUB:
2863 case ISD::FMUL:
2864 case ISD::FDIV:
2865 case ISD::FREM:
2867 if (Opcode == ISD::FADD) {
2876 } else if (Opcode == ISD::FSUB) {
2881 } else if (Opcode == ISD::FMUL) {
2905 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match.
2911 case ISD::SHL:
2912 case ISD::SRA:
2913 case ISD::SRL:
2914 case ISD::ROTL:
2915 case ISD::ROTR:
2938 case ISD::FP_ROUND_INREG: {
2954 case ISD::FP_ROUND:
2961 case ISD::AssertSext:
2962 case ISD::AssertZext: {
2974 case ISD::SIGN_EXTEND_INREG: {
2997 case ISD::EXTRACT_VECTOR_ELT:
2999 if (N1.getOpcode() == ISD::UNDEF)
3005 N1.getOpcode() == ISD::CONCAT_VECTORS &&
3009 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
3017 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) {
3031 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) {
3046 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2);
3050 case ISD::EXTRACT_ELEMENT:
3060 ISD::BUILD_PAIR)
3071 case ISD::EXTRACT_SUBVECTOR: {
3118 case ISD::FADD:
3123 case ISD::FSUB:
3128 case ISD::FMUL:
3133 case ISD::FDIV:
3138 case ISD::FREM :
3143 case ISD::FCOPYSIGN:
3150 if (Opcode == ISD::FP_ROUND) {
3162 if (N1.getOpcode() == ISD::UNDEF) {
3167 case ISD::FP_ROUND_INREG:
3168 case ISD::SIGN_EXTEND_INREG:
3169 case ISD::SUB:
3170 case ISD::FSUB:
3171 case ISD::FDIV:
3172 case ISD::FREM:
3173 case ISD::SRA:
3175 case ISD::UDIV:
3176 case ISD::SDIV:
3177 case ISD::UREM:
3178 case ISD::SREM:
3179 case ISD::SRL:
3180 case ISD::SHL:
3191 if (N2.getOpcode() == ISD::UNDEF) {
3193 case ISD::XOR:
3194 if (N1.getOpcode() == ISD::UNDEF)
3199 case ISD::ADD:
3200 case ISD::ADDC:
3201 case ISD::ADDE:
3202 case ISD::SUB:
3203 case ISD::UDIV:
3204 case ISD::SDIV:
3205 case ISD::UREM:
3206 case ISD::SREM:
3208 case ISD::FADD:
3209 case ISD::FSUB:
3210 case ISD::FMUL:
3211 case ISD::FDIV:
3212 case ISD::FREM:
3216 case ISD::MUL:
3217 case ISD::AND:
3218 case ISD::SRL:
3219 case ISD::SHL:
3225 case ISD::OR:
3231 case ISD::SRA:
3265 case ISD::FMA: {
3280 case ISD::CONCAT_VECTORS:
3283 if (N1.getOpcode() == ISD::BUILD_VECTOR &&
3284 N2.getOpcode() == ISD::BUILD_VECTOR &&
3285 N3.getOpcode() == ISD::BUILD_VECTOR) {
3290 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
3293 case ISD::SETCC: {
3299 case ISD::SELECT:
3308 case ISD::VECTOR_SHUFFLE:
3310 case ISD::INSERT_SUBVECTOR: {
3334 case ISD::BITCAST:
3398 return getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other,
3406 assert(Value.getOpcode() != ISD::UNDEF);
3417 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value);
3422 Value = DAG.getNode(ISD::MUL, dl, VT, Value, DAG.getConstant(Magic, VT));
3442 return DAG.getNode(ISD::BITCAST, dl, VT,
3476 return DAG.getNode(ISD::ADD, dl,
3485 if (Src.getOpcode() == ISD::GlobalAddress)
3487 else if (Src.getOpcode() == ISD::ADD &&
3488 Src.getOperand(0).getOpcode() == ISD::GlobalAddress &&
3489 Src.getOperand(1).getOpcode() == ISD::Constant) {
3558 if (TLI.isOperationLegalOrCustom(ISD::STORE, NewVT) &&
3562 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::f64) &&
3612 if (Src.getOpcode() == ISD::UNDEF)
3703 Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain,
3718 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3730 if (Src.getOpcode() == ISD::UNDEF)
3784 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3799 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3809 if (Src.getOpcode() == ISD::UNDEF)
3869 Value = DAG.getNode(ISD::TRUNCATE, dl, VT, MemSetValue);
3883 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4054 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
4056 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
4096 if (Opcode != ISD::ATOMIC_STORE)
4098 if (Opcode != ISD::ATOMIC_LOAD)
4114 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
4156 if (Opcode != ISD::ATOMIC_STORE)
4158 if (Opcode != ISD::ATOMIC_LOAD)
4175 assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
4176 Opcode == ISD::ATOMIC_LOAD_SUB ||
4177 Opcode == ISD::ATOMIC_LOAD_AND ||
4178 Opcode == ISD::ATOMIC_LOAD_OR ||
4179 Opcode == ISD::ATOMIC_LOAD_XOR ||
4180 Opcode == ISD::ATOMIC_LOAD_NAND ||
4181 Opcode == ISD::ATOMIC_LOAD_MIN ||
4182 Opcode == ISD::ATOMIC_LOAD_MAX ||
4183 Opcode == ISD::ATOMIC_LOAD_UMIN ||
4184 Opcode == ISD::ATOMIC_LOAD_UMAX ||
4185 Opcode == ISD::ATOMIC_SWAP ||
4186 Opcode == ISD::ATOMIC_STORE) &&
4191 SDVTList VTs = Opcode == ISD::ATOMIC_STORE ? getVTList(MVT::Other) :
4229 if (Opcode != ISD::ATOMIC_STORE)
4231 if (Opcode != ISD::ATOMIC_LOAD)
4248 assert(Opcode == ISD::ATOMIC_LOAD && "Invalid Atomic Op");
4278 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps),
4321 assert((Opcode == ISD::INTRINSIC_VOID ||
4322 Opcode == ISD::INTRINSIC_W_CHAIN ||
4323 Opcode == ISD::PREFETCH ||
4324 Opcode == ISD::LIFETIME_START ||
4325 Opcode == ISD::LIFETIME_END ||
4327 (int)Opcode >= ISD::FIRST_TARGET_MEMORY_OPCODE)) &&
4363 if (Ptr.getOpcode() != ISD::ADD ||
4381 if (OffsetOp.getOpcode() == ISD::UNDEF)
4388 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
4421 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
4426 ExtType = ISD::NON_EXTLOAD;
4427 } else if (ExtType == ISD::NON_EXTLOAD) {
4442 bool Indexed = AM != ISD::UNINDEXED;
4443 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) &&
4450 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
4476 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
4481 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,
4487 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef,
4495 SDValue Offset, ISD::MemIndexedMode AM) {
4497 assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
4541 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
4543 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, MMO->isVolatile(),
4551 SDNode *N = new (NodeAllocator) StoreSDNode(Ops, dl.getIROrder(), dl.getDebugLoc(), VTs, ISD::UNINDEXED,
4609 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
4611 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, MMO->isVolatile(),
4619 SDNode *N = new (NodeAllocator) StoreSDNode(Ops, dl.getIROrder(), dl.getDebugLoc(), VTs, ISD::UNINDEXED,
4628 SDValue Offset, ISD::MemIndexedMode AM) {
4630 assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
4635 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
4657 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 4);
4688 case ISD::SELECT_CC: {
4698 case ISD::BR_CC: {
4756 case ISD::SRA_PARTS:
4757 case ISD::SRL_PARTS:
4758 case ISD::SHL_PARTS:
4759 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4762 else if (N3.getOpcode() == ISD::AND)
5859 assert(AllNodes.front().getOpcode() == ISD::EntryToken &&
5922 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile(),
5935 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile(),
6055 if (getOpcode() == ISD::TokenFactor) {
6140 Operands[j] = getNode(ISD::EXTRACT_VECTOR_ELT, dl,
6155 case ISD::VSELECT:
6156 Scalars.push_back(getNode(ISD::SELECT, dl, EltVT,
6159 case ISD::SHL:
6160 case ISD::SRA:
6161 case ISD::SRL:
6162 case ISD::ROTL:
6163 case ISD::ROTR:
6168 case ISD::SIGN_EXTEND_INREG:
6169 case ISD::FP_ROUND_INREG: {
6181 return getNode(ISD::BUILD_VECTOR, dl,
6200 if (Loc.getOpcode() == ISD::FrameIndex) {
6201 if (BaseLoc.getOpcode() != ISD::FrameIndex)
6299 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared
6311 if (OpVal.getOpcode() == ISD::UNDEF)
