Lines Matching refs:OPCODE
974 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
977 switch (Opcode) {
980 #define HANDLE_INST(NUM, OPCODE, CLASS) \
981 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
2653 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2656 setValue(&I, DAG.getNode(OpCode, getCurSDLoc(),
2660 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2688 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(),
2717 ISD::CondCode Opcode = getICmpCondCode(predicate);
2720 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2748 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2752 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
4906 unsigned Opcode;
4909 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4910 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4911 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4912 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4913 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4914 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4915 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4916 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4917 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4920 setValue(&I, DAG.getNode(Opcode, sdl,
5196 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5198 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops, 2);
5530 /// operation (as expected), translate it to an SDNode with the specified opcode
5533 unsigned Opcode) {
5542 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
