Lines Matching refs:ISD
104 ISD::CondCode &CCCode,
112 case ISD::SETEQ:
113 case ISD::SETOEQ:
117 case ISD::SETNE:
118 case ISD::SETUNE:
122 case ISD::SETGE:
123 case ISD::SETOGE:
127 case ISD::SETLT:
128 case ISD::SETOLT:
132 case ISD::SETLE:
133 case ISD::SETOLE:
137 case ISD::SETGT:
138 case ISD::SETOGT:
142 case ISD::SETUO:
146 case ISD::SETO:
154 case ISD::SETONE:
159 case ISD::SETUGT:
163 case ISD::SETUGE:
167 case ISD::SETULT:
171 case ISD::SETULE:
175 case ISD::SETUEQ:
190 SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
194 NewLHS = DAG.getNode(ISD::SETCC, dl,
197 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
269 // FIXME: ISD::SELECT, ISD::SELECT_CC
272 case ISD::XOR:
273 case ISD::AND:
274 case ISD::OR: {
278 if (Op.getOpcode() == ISD::XOR &&
331 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
333 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
336 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
379 if (Op.getOpcode() != ISD::UNDEF)
388 case ISD::Constant:
393 case ISD::AND:
441 case ISD::OR:
475 case ISD::XOR:
499 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
517 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
545 case ISD::SELECT:
563 case ISD::SELECT_CC:
581 case ISD::SHL:
593 if (InOp.getOpcode() == ISD::SRL &&
597 unsigned Opc = ISD::SHL;
601 Opc = ISD::SRL;
618 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
623 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
628 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
632 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
643 case ISD::SRL:
657 if (InOp.getOpcode() == ISD::SHL &&
661 unsigned Opc = ISD::SRL;
665 Opc = ISD::SHL;
687 case ISD::SRA:
694 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
726 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
734 case ISD::SIGN_EXTEND_INREG: {
750 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
797 case ISD::ZERO_EXTEND: {
806 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
819 case ISD::SIGN_EXTEND: {
828 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
846 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
860 case ISD::ANY_EXTEND: {
872 case ISD::TRUNCATE: {
890 case ISD::SRL:
894 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
915 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
918 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
930 case ISD::AssertZext: {
944 case ISD::BITCAST:
952 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
953 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
958 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
961 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
964 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
970 case ISD::ADD:
971 case ISD::MUL:
972 case ISD::SUB: {
1010 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1011 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1012 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1013 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1024 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1025 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1026 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1027 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1040 if (Val.getOpcode() == ISD::SHL)
1048 if (Val.getOpcode() == ISD::SRL)
1070 ISD::CondCode Cond, bool foldBooleans,
1077 case ISD::SETFALSE:
1078 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1079 case ISD::SETTRUE:
1080 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1086 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1094 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1095 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1096 N0.getOperand(1).getOpcode() == ISD::Constant) {
1099 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1101 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1104 Cond = ISD::SETNE;
1108 Cond = ISD::SETEQ;
1118 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1121 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1129 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1130 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1132 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1133 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1142 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1145 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1149 } else if (N0->getOpcode() == ISD::AND) {
1158 ISD::ZEXTLOAD) {
1168 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1170 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
1181 N0.getOpcode() == ISD::AND && C1 == 0 &&
1194 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1220 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1227 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1236 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1244 case ISD::SETUGT:
1245 case ISD::SETUGE:
1246 case ISD::SETEQ: return DAG.getConstant(0, VT);
1247 case ISD::SETULT:
1248 case ISD::SETULE:
1249 case ISD::SETNE: return DAG.getConstant(1, VT);
1250 case ISD::SETGT:
1251 case ISD::SETGE:
1254 case ISD::SETLT:
1255 case ISD::SETLE:
1265 case ISD::SETEQ:
1266 case ISD::SETNE:
1267 case ISD::SETUGT:
1268 case ISD::SETUGE:
1269 case ISD::SETULT:
1270 case ISD::SETULE: {
1273 (isOperationLegal(ISD::SETCC, newVT) &&
1283 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1284 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1293 return DAG.getConstant(Cond == ISD::SETNE, VT);
1301 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1314 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1316 if (N0.getOpcode() == ISD::SETCC &&
1318 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1320 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1322 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1323 CC = ISD::getSetCCInverse(CC,
1328 if ((N0.getOpcode() == ISD::XOR ||
1329 (N0.getOpcode() == ISD::AND &&
1330 N0.getOperand(0).getOpcode() == ISD::XOR &&
1342 if (N0.getOpcode() == ISD::XOR)
1345 assert(N0.getOpcode() == ISD::AND &&
1346 N0.getOperand(0).getOpcode() == ISD::XOR);
1348 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1354 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1360 if (Op0.getOpcode() == ISD::TRUNCATE)
1363 if ((Op0.getOpcode() == ISD::XOR) &&
1364 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1365 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1367 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1371 if (Op0.getOpcode() == ISD::AND &&
1376 Op0 = DAG.getNode(ISD::AND, dl, VT,
1377 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1380 Op0 = DAG.getNode(ISD::AND, dl, VT,
1381 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1386 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1388 if (Op0.getOpcode() == ISD::AssertZext &&
1392 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1398 if (ISD::isSignedIntSetCC(Cond)) {
1407 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1412 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1415 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1420 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1423 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1425 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1427 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1429 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1433 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1434 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1436 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1437 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1440 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1443 ISD::SETEQ);
1445 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1448 ISD::SETEQ);
1454 if (Cond == ISD::SETUGT &&
1458 ISD::SETLT);
1461 if (Cond == ISD::SETULT &&
1466 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1470 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1473 N0.getOpcode() == ISD::AND)
1478 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1481 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1482 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1485 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1489 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1490 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1499 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1500 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1509 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1515 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1516 Cond == ISDISD::SETUGT) {
1517 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1524 ISD::CondCode NewCond = Cond;
1528 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1537 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1555 switch (ISD::getUnorderedFlavor(Cond)) {
1570 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1581 if (Cond == ISD::SETOEQ &&
1582 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1583 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1584 if (Cond == ISD::SETUEQ &&
1585 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1586 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1587 if (Cond == ISD::SETUNE &&
1588 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1589 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1590 if (Cond == ISD::SETONE &&
1591 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1592 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1594 if (Cond == ISD::SETOEQ &&
1595 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1596 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1597 if (Cond == ISD::SETUEQ &&
1598 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1599 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1600 if (Cond == ISD::SETUNE &&
1601 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1602 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1603 if (Cond == ISD::SETONE &&
1604 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1605 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1618 EqVal = ISD::isTrueWhenEqual(Cond);
1621 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1629 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1632 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1636 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1642 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1644 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1645 N0.getOpcode() == ISD::XOR) {
1670 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1678 if (N0.getOpcode() == ISD::XOR)
1692 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1720 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1722 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1732 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1733 N1.getOpcode() == ISD::XOR) {
1743 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1745 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1758 if (N0.getOpcode() == ISD::AND)
1761 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1766 if (N1.getOpcode() == ISD::AND)
1769 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1781 case ISD::SETEQ: // X == Y -> ~(X^Y)
1782 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1787 case ISD::SETNE: // X != Y --> (X^Y)
1788 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1790 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1791 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1793 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1797 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
1798 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
1800 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1804 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
1805 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
1807 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
1811 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
1812 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
1814 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
1821 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
1841 if (N->getOpcode() == ISD::ADD) {
1939 if (Op.getOpcode() == ISD::BasicBlock) {
1954 if (Op.getOpcode() == ISD::ADD) {
2454 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
2464 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2467 /// \brief Given an ISD::SDIV node expressing a divide by constant,
2488 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2489 isOperationLegalOrCustom(ISD::MULHS, VT))
2490 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2492 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2493 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2494 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2501 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2507 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2513 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2520 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2524 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2527 /// \brief Given an ISD::UDIV node expressing a divide by constant,
2553 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2565 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2566 isOperationLegalOrCustom(ISD::MULHU, VT))
2567 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
2568 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2569 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2570 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2580 return DAG.getNode(ISD::SRL, dl, VT, Q,
2583 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2586 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2590 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2593 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
