Lines Matching refs:DefMI
156 const MachineInstr *DefMI, unsigned DefOperIdx,
160 return TII->defaultDefLatency(&SchedModel, DefMI);
165 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx,
169 unsigned DefClass = DefMI->getDesc().getSchedClass();
176 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
184 TII->defaultDefLatency(&SchedModel, DefMI));
188 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
189 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
212 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
213 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()) {
217 << *DefMI;
224 return DefMI->isTransient() ? 0 : TII->defaultDefLatency(&SchedModel, DefMI);
251 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
265 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
266 const MachineFunction &MF = *DefMI->getParent()->getParent();
269 return computeInstrLatency(DefMI);
274 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);