Lines Matching refs:NewMIs
1200 SmallVector<MachineInstr *, 2> NewMIs;
1203 NewMIs)) {
1207 assert(NewMIs.size() == 2 &&
1210 NewMIs[1]->addRegisterKilled(Reg, TRI);
1214 MBB->insert(mi, NewMIs[0]);
1215 MBB->insert(mi, NewMIs[1]);
1217 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1218 << "2addr: NEW INST: " << *NewMIs[1]);
1221 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1222 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1223 MachineBasicBlock::iterator NewMI = NewMIs[1];
1229 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1239 if (NewMIs[0]->killsRegister(MO.getReg()))
1240 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
1242 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1244 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
1248 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1249 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
1251 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1253 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
1258 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
1274 MachineBasicBlock::iterator Begin(NewMIs[0]);
1275 MachineBasicBlock::iterator End(NewMIs[1]);
1279 mi = NewMIs[1];
1285 NewMIs[0]->eraseFromParent();
1286 NewMIs[1]->eraseFromParent();
