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Lines Matching refs:RegA

105   bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
111 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
115 unsigned RegA, unsigned RegB, unsigned Dist);
495 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
496 if (RegA == RegB)
498 if (!RegA || !RegB)
500 return TRI->regsOverlap(RegA, RegB);
508 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
544 unsigned ToRegA = getMappedReg(regA, DstRegMap);
594 unsigned RegA = MI->getOperand(0).getReg();
595 SrcRegMap[RegA] = FromRegC;
604 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
614 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
623 unsigned RegA, unsigned RegB,
654 SrcRegMap.erase(RegA);
1102 unsigned regA = MI.getOperand(DstIdx).getReg();
1109 if (TargetRegisterInfo::isVirtualRegister(regA))
1110 scanUses(regA);
1131 else if (isProfitableToCommute(regA, regB, regC, &MI, Dist)) {
1159 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1161 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1221 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1357 unsigned RegA = DstMO.getReg();
1363 if (RegA == RegB) {
1370 LastCopiedReg = RegA;
1382 MI->getOperand(i).getReg() != RegA);
1387 TII->get(TargetOpcode::COPY), RegA).addReg(RegB);
1398 if (TargetRegisterInfo::isVirtualRegister(RegA)) {
1399 LiveInterval &LI = LIS->getInterval(RegA);
1417 // Make sure regA is a legal regclass for the SrcIdx operand.
1418 if (TargetRegisterInfo::isVirtualRegister(RegA) &&
1420 MRI->constrainRegClass(RegA, MRI->getRegClass(RegB));
1422 MO.setReg(RegA);
1425 SrcRegMap[RegA] = RegB;