Lines Matching full:setcc
114 setOperationAction(ISD::SETCC, MVT::i32, Custom);
115 setOperationAction(ISD::SETCC, MVT::i64, Custom);
116 setOperationAction(ISD::SETCC, MVT::f32, Custom);
117 setOperationAction(ISD::SETCC, MVT::f64, Custom);
232 setOperationAction(ISD::SETCC, MVT::f128, Custom);
285 setOperationAction(ISD::SETCC, MVT::v8i8, Custom);
286 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
287 setOperationAction(ISD::SETCC, MVT::v4i16, Custom);
288 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
289 setOperationAction(ISD::SETCC, MVT::v2i32, Custom);
290 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
291 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
292 setOperationAction(ISD::SETCC, MVT::v2f32, Custom);
293 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
294 setOperationAction(ISD::SETCC, MVT::v2f64, Custom);
815 case AArch64ISD::SETCC: return "AArch64ISD::SETCC";
1680 return DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
1758 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
1807 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
1810 Chain, SetCC, A64cc, DestBB);
1815 A64BR_CC, SetCC, A64cc, DestBB);
2252 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2256 SetCC, IfTrue, IfFalse, A64cc);
2261 SetCC, IfTrue, A64SELECT_CC, A64cc);
2281 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
2497 // (SETCC lhs, rhs, condcode)
2517 "Unexpected setcc expansion!");
2540 SDValue CmpOp = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2662 case ISD::SETCC: return LowerSETCC(Op, DAG);
