Lines Matching refs:CondCode
628 unsigned CondCode = MI->getOperand(3).getImm();
654 .addImm(CondCode)
1595 static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) {
1623 ISD::CondCode CC, SDValue &A64cc,
1678 A64CC::CondCodes CondCode = IntCCToA64CC(CC);
1679 A64cc = DAG.getConstant(CondCode, MVT::i32);
1684 static A64CC::CondCodes FPCCToA64CC(ISD::CondCode CC,
1686 A64CC::CondCodes CondCode = A64CC::Invalid;
1692 case ISD::SETOEQ: CondCode = A64CC::EQ; break;
1694 case ISD::SETOGT: CondCode = A64CC::GT; break;
1696 case ISD::SETOGE: CondCode = A64CC::GE; break;
1697 case ISD::SETOLT: CondCode = A64CC::MI; break;
1698 case ISD::SETOLE: CondCode = A64CC::LS; break;
1699 case ISD::SETONE: CondCode = A64CC::MI; Alternative = A64CC::GT; break;
1700 case ISD::SETO: CondCode = A64CC::VC; break;
1701 case ISD::SETUO: CondCode = A64CC::VS; break;
1702 case ISD::SETUEQ: CondCode = A64CC::EQ; Alternative = A64CC::VS; break;
1703 case ISD::SETUGT: CondCode = A64CC::HI; break;
1704 case ISD::SETUGE: CondCode = A64CC::PL; break;
1706 case ISD::SETULT: CondCode = A64CC::LT; break;
1708 case ISD::SETULE: CondCode = A64CC::LE; break;
1710 case ISD::SETUNE: CondCode = A64CC::NE; break;
1712 return CondCode;
1767 // (BR_CC chain, condcode, lhs, rhs, dest)
1772 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1804 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
1805 CondCode = FPCCToA64CC(CC, Alternative);
1806 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
2212 // (SELECT_CC lhs, rhs, iftrue, iffalse, condcode)
2220 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2249 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
2250 CondCode = FPCCToA64CC(CC, Alternative);
2251 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
2294 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2323 // If LHS is the zero value, swap operands and CondCode.
2330 // Ensure valid CondCode for Compare Mask against Zero instruction:
2343 // Ensure valid CondCode for Compare Mask instr: EQ, GE, GT, UGE, UGT.
2389 // If LHS is the zero value, swap operands and CondCode.
2411 // Ensure valid CondCode for FP Compare Mask against Zero instruction:
2413 // And ensure valid CondCode for FP Compare Mask instruction: EQ, GE, GT.
2497 // (SETCC lhs, rhs, condcode)
2503 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2537 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
2538 CondCode = FPCCToA64CC(CC, Alternative);
2539 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
