Lines Matching refs:ISD
76 setTargetDAGCombine(ISD::OR);
78 setTargetDAGCombine(ISD::AND);
79 setTargetDAGCombine(ISD::SRA);
82 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
87 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
88 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
89 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
92 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
93 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
97 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
98 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
99 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
100 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
102 setOperationAction(ISD::SELECT, MVT::i32, Custom);
103 setOperationAction(ISD::SELECT, MVT::i64, Custom);
104 setOperationAction(ISD::SELECT, MVT::f32, Custom);
105 setOperationAction(ISD::SELECT, MVT::f64, Custom);
107 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
108 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
109 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
110 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
112 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
114 setOperationAction(ISD::SETCC, MVT::i32, Custom);
115 setOperationAction(ISD::SETCC, MVT::i64, Custom);
116 setOperationAction(ISD::SETCC, MVT::f32, Custom);
117 setOperationAction(ISD::SETCC, MVT::f64, Custom);
119 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
120 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
121 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
123 setOperationAction(ISD::VASTART, MVT::Other, Custom);
124 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
125 setOperationAction(ISD::VAEND, MVT::Other, Expand);
126 setOperationAction(ISD::VAARG, MVT::Other, Expand);
128 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
130 setOperationAction(ISD::ROTL, MVT::i32, Expand);
131 setOperationAction(ISD::ROTL, MVT::i64, Expand);
133 setOperationAction(ISD::UREM, MVT::i32, Expand);
134 setOperationAction(ISD::UREM, MVT::i64, Expand);
135 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
136 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
138 setOperationAction(ISD::SREM, MVT::i32, Expand);
139 setOperationAction(ISD::SREM, MVT::i64, Expand);
140 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
141 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
143 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
144 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
147 setOperationAction(ISD::FABS, MVT::f32, Legal);
148 setOperationAction(ISD::FABS, MVT::f64, Legal);
150 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
151 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
153 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
154 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
156 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
157 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
159 setOperationAction(ISD::FNEG, MVT::f32, Legal);
160 setOperationAction(ISD::FNEG, MVT::f64, Legal);
162 setOperationAction(ISD::FRINT, MVT::f32, Legal);
163 setOperationAction(ISD::FRINT, MVT::f64, Legal);
165 setOperationAction(ISD::FSQRT, MVT::f32, Legal);
166 setOperationAction(ISD::FSQRT, MVT::f64, Legal);
168 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
169 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
171 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
172 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
173 setOperationAction(ISD::ConstantFP, MVT::f128, Legal);
176 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
177 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
179 setOperationAction(ISD::FCOS, MVT::f32, Expand);
180 setOperationAction(ISD::FCOS, MVT::f64, Expand);
182 setOperationAction(ISD::FEXP, MVT::f32, Expand);
183 setOperationAction(ISD::FEXP, MVT::f64, Expand);
185 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
186 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
188 setOperationAction(ISD::FLOG, MVT::f32, Expand);
189 setOperationAction(ISD::FLOG, MVT::f64, Expand);
191 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
192 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
194 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
195 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
197 setOperationAction(ISD::FPOW, MVT::f32, Expand);
198 setOperationAction(ISD::FPOW, MVT::f64, Expand);
200 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
201 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
203 setOperationAction(ISD::FREM, MVT::f32, Expand);
204 setOperationAction(ISD::FREM, MVT::f64, Expand);
206 setOperationAction(ISD::FSIN, MVT::f32, Expand);
207 setOperationAction(ISD::FSIN, MVT::f64, Expand);
209 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
210 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
214 setOperationAction(ISD::FABS, MVT::f128, Expand);
215 setOperationAction(ISD::FADD, MVT::f128, Custom);
216 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
217 setOperationAction(ISD::FCOS, MVT::f128, Expand);
218 setOperationAction(ISD::FDIV, MVT::f128, Custom);
219 setOperationAction(ISD::FMA, MVT::f128, Expand);
220 setOperationAction(ISD::FMUL, MVT::f128, Custom);
221 setOperationAction(ISD::FNEG, MVT::f128, Expand);
222 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand);
223 setOperationAction(ISD::FP_ROUND, MVT::f128, Expand);
224 setOperationAction(ISD::FPOW, MVT::f128, Expand);
225 setOperationAction(ISD::FREM, MVT::f128, Expand);
226 setOperationAction(ISD::FRINT, MVT::f128, Expand);
227 setOperationAction(ISD::FSIN, MVT::f128, Expand);
228 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
229 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
230 setOperationAction(ISD::FSUB, MVT::f128, Custom);
231 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
232 setOperationAction(ISD::SETCC, MVT::f128, Custom);
233 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
234 setOperationAction(ISD::SELECT, MVT::f128, Expand);
235 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
236 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
240 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
241 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
242 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
243 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
244 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
245 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
246 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
247 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
248 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
249 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
250 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
251 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
252 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
253 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
258 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
259 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
260 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
273 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
274 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
275 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
276 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
277 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
278 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
279 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
280 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
281 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
282 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
283 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
285 setOperationAction(ISD::SETCC, MVT::v8i8, Custom);
286 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
287 setOperationAction(ISD::SETCC, MVT::v4i16, Custom);
288 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
289 setOperationAction(ISD::SETCC, MVT::v2i32, Custom);
290 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
291 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
292 setOperationAction(ISD::SETCC, MVT::v2f32, Custom);
293 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
294 setOperationAction(ISD::SETCC, MVT::v2f64, Custom);
855 ISD::ArgFlagsTy ArgFlags, CCState &State) {
906 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
926 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
940 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
949 const SmallVectorImpl<ISD::InputArg> &Ins,
968 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1008 ArgValue = DAG.getNode(ISD::BITCAST,dl, VA.getValVT(), ArgValue);
1063 const SmallVectorImpl<ISD::OutputArg> &Outs,
1112 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1115 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1139 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1141 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1215 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1249 ISD::BITCAST, dl, VA.getLocVT(), Arg);
1281 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1305 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1401 const SmallVectorImpl<ISD::InputArg> &Ins,
1426 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1433 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
1449 const SmallVectorImpl<ISD::OutputArg> &Outs,
1451 const SmallVectorImpl<ISD::InputArg> &Ins,
1591 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other,
1595 static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) {
1597 case ISD::SETEQ: return A64CC::EQ;
1598 case ISD::SETGT: return A64CC::GT;
1599 case ISD::SETGE: return A64CC::GE;
1600 case ISD::SETLT: return A64CC::LT;
1601 case ISD::SETLE: return A64CC::LE;
1602 case ISD::SETNE: return A64CC::NE;
1603 case ISD::SETUGT: return A64CC::HI;
1604 case ISD::SETUGE: return A64CC::HS;
1605 case ISD::SETULT: return A64CC::LO;
1606 case ISD::SETULE: return A64CC::LS;
1623 ISD::CondCode CC, SDValue &A64cc,
1646 case ISD::SETLT:
1647 case ISD::SETGE:
1649 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1653 case ISD::SETULT:
1654 case ISD::SETUGE:
1656 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1660 case ISD::SETLE:
1661 case ISD::SETGT:
1663 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1667 case ISD::SETULE:
1668 case ISD::SETUGT:
1670 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1684 static A64CC::CondCodes FPCCToA64CC(ISD::CondCode CC,
1691 case ISD::SETEQ:
1692 case ISD::SETOEQ: CondCode = A64CC::EQ; break;
1693 case ISD::SETGT:
1694 case ISD::SETOGT: CondCode = A64CC::GT; break;
1695 case ISD::SETGE:
1696 case ISD::SETOGE: CondCode = A64CC::GE; break;
1697 case ISD::SETOLT: CondCode = A64CC::MI; break;
1698 case ISD::SETOLE: CondCode = A64CC::LS; break;
1699 case ISD::SETONE: CondCode = A64CC::MI; Alternative = A64CC::GT; break;
1700 case ISD::SETO: CondCode = A64CC::VC; break;
1701 case ISD::SETUO: CondCode = A64CC::VS; break;
1702 case ISD::SETUEQ: CondCode = A64CC::EQ; Alternative = A64CC::VS; break;
1703 case ISD::SETUGT: CondCode = A64CC::HI; break;
1704 case ISD::SETUGE: CondCode = A64CC::PL; break;
1705 case ISD::SETLT:
1706 case ISD::SETULT: CondCode = A64CC::LT; break;
1707 case ISD::SETLE:
1708 case ISD::SETULE: CondCode = A64CC::LE; break;
1709 case ISD::SETNE:
1710 case ISD::SETUNE: CondCode = A64CC::NE; break;
1755 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
1760 DAG.getCondCode(ISD::SETNE));
1772 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1786 CC = ISD::SETNE;
1927 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr,
1961 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr,
2008 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalRef,
2164 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2220 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2231 CC = ISD::SETNE;
2279 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
2283 DAG.getCondCode(ISD::SETNE));
2294 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2304 if (CC == ISD::SETNE) {
2305 if (((LHS.getOpcode() == ISD::AND) &&
2306 ISD::isBuildVectorAllZeros(RHS.getNode())) ||
2307 ((RHS.getOpcode() == ISD::AND) &&
2308 ISD::isBuildVectorAllZeros(LHS.getNode()))) {
2310 SDValue AndOp = (LHS.getOpcode() == ISD::AND) ? LHS : RHS;
2311 SDValue NewLHS = DAG.getNode(ISD::BITCAST, DL, VT, AndOp.getOperand(0));
2312 SDValue NewRHS = DAG.getNode(ISD::BITCAST, DL, VT, AndOp.getOperand(1));
2319 if ((ISD::isBuildVectorAllZeros(RHS.getNode()) ||
2320 ISD::isBuildVectorAllZeros(LHS.getNode())) &&
2324 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
2332 if (ISD::SETNE == CC) {
2334 CC = ISD::SETEQ;
2348 case ISD::SETEQ:
2349 case ISD::SETGT:
2350 case ISD::SETGE:
2351 case ISD::SETUGT:
2352 case ISD::SETUGE:
2354 case ISD::SETNE:
2356 CC = ISD::SETEQ;
2358 case ISD::SETULT:
2359 case ISD::SETULE:
2360 case ISD::SETLT:
2361 case ISD::SETLE:
2386 if (ISD::isBuildVectorAllZeros(RHS.getNode()) ||
2387 ISD::isBuildVectorAllZeros(LHS.getNode())) {
2390 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
2417 case ISD::SETUNE:
2418 case ISD::SETNE:
2420 case ISD::SETOEQ:
2421 case ISD::SETEQ:
2422 CC = ISD::SETEQ;
2424 case ISD::SETOLT:
2425 case ISD::SETLT:
2426 CC = ISD::SETLT;
2429 case ISD::SETOGT:
2430 case ISD::SETGT:
2431 CC = ISD::SETGT;
2433 case ISD::SETOLE:
2434 case ISD::SETLE:
2435 CC = ISD::SETLE;
2438 case ISD::SETOGE:
2439 case ISD::SETGE:
2440 CC = ISD::SETGE;
2442 case ISD::SETUGE:
2444 CC = ISD::SETLT;
2447 case ISD::SETULE:
2449 CC = ISD::SETGT;
2451 case ISD::SETUGT:
2453 CC = ISD::SETLE;
2456 case ISD::SETULT:
2458 CC = ISD::SETGE;
2460 case ISD::SETUEQ:
2462 case ISD::SETONE:
2465 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGT));
2466 CC = ISD::SETLT;
2469 case ISD::SETUO:
2471 case ISD::SETO:
2474 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGE));
2475 CC = ISD::SETLT;
2489 NeonCmp = DAG.getNode(ISD::OR, DL, VT, NeonCmp, NeonCmpAlt);
2503 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2593 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2597 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
2609 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2613 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
2622 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2629 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
2635 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
2643 case ISD::FADD: return LowerF128ToCall(Op, DAG, RTLIB::ADD_F128);
2644 case ISD::FSUB: return LowerF128ToCall(Op, DAG, RTLIB::SUB_F128);
2645 case ISD::FMUL: return LowerF128ToCall(Op, DAG, RTLIB::MUL_F128);
2646 case ISD::FDIV: return LowerF128ToCall(Op, DAG, RTLIB::DIV_F128);
2647 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, true);
2648 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG, false);
2649 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG, true);
2650 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG, false);
2651 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
2652 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
2654 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2655 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
2656 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
2657 case ISD::GlobalAddress: return LowerGlobalAddressELF(Op, DAG);
2658 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2659 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2660 case ISD::SELECT: return LowerSELECT(Op, DAG);
2661 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2662 case ISD::SETCC: return LowerSETCC(Op, DAG);
2663 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
2664 case ISD::VASTART: return LowerVASTART(Op, DAG);
2665 case ISD::BUILD_VECTOR:
2836 if (Shift.getOpcode() != ISD::SRL)
2874 if (MaskedVal.getOpcode() == ISD::SHL &&
2878 } else if (MaskedVal.getOpcode() == ISD::SRL &&
2885 MaskedVal = DAG.getNode(ISD::SRL, DL, VT, MaskedVal,
2890 MaskedVal = DAG.getNode(ISD::SHL, DL, VT, MaskedVal,
2903 if (N.getOpcode() == ISD::ZERO_EXTEND) {
2908 if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(N.getOperand(1))) {
2935 assert(N->getOpcode() == ISD::OR && "Unexpected root");
2940 if (LHS.getOpcode() != ISD::AND)
2952 if (RHS.getOpcode() != ISD::AND)
2994 return DAG.getNode(ISD::AND, DL, VT, BFI,
3030 if (PossExtraMask.getOpcode() != ISD::AND ||
3048 OldBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, OldBFIVal);
3049 NewBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, NewBFIVal);
3064 return DAG.getNode(ISD::AND, DL, VT, BFI,
3072 if (N.getOpcode() == ISD::SHL)
3074 else if (N.getOpcode() == ISD::SRL)
3098 assert(N->getOpcode() == ISD::OR && "Unexpected root");
3133 /// Target-specific dag combine xforms for ISD::OR
3167 if (N0.getOpcode() != ISD::AND)
3171 if (N1.getOpcode() != ISD::AND)
3193 return DAG.getNode(ISD::BITCAST, DL, VT, Result);
3201 /// Target-specific dag combine xforms for ISD::SRA
3220 if (Shift.getOpcode() != ISD::SHL)
3244 case ISD::AND: return PerformANDCombine(N, DCI);
3245 case ISD::OR: return PerformORCombine(N, DCI, getSubtarget());
3246 case ISD::SRA: return PerformSRACombine(N, DCI);
3307 return DAG.getNode(ISD::BITCAST, DL, VT, NeonMov);
3321 return DAG.getNode(ISD::BITCAST, DL, VT, NeonMov);
