Lines Matching refs:Other
88 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
89 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
112 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
119 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
123 setOperationAction(ISD::VASTART, MVT::Other, Custom);
124 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
125 setOperationAction(ISD::VAEND, MVT::Other, Expand);
126 setOperationAction(ISD::VAARG, MVT::Other, Expand);
391 // Operand order needs to go the other way for NAND.
940 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
1130 return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other,
1171 // On AArch64 (and all other architectures I'm aware of) the most this has to
1302 // other. Combining them with this TokenFactor notes that fact for the rest of
1305 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1373 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1455 // changing. That's not true for other conventions so they will have to opt in
1591 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other,
1762 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other, Chain,
1797 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
1809 SDValue A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
1814 A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
2064 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2635 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
2714 // can't handle any other
2781 // can't handle any other
