Lines Matching refs:VA
967 CCValAssign &VA = ArgLocs[i];
978 VA.getLocMemOffset(),
984 } else if (VA.isRegLoc()) {
985 MVT RegVT = VA.getLocVT();
987 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
990 } else { // VA.isRegLoc()
991 assert(VA.isMemLoc());
993 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
994 VA.getLocMemOffset(), true);
997 ArgValue = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1004 switch (VA.getLocInfo()) {
1008 ArgValue = DAG.getNode(ISD::BITCAST,dl, VA.getValVT(), ArgValue);
1013 unsigned DestSize = VA.getValVT().getSizeInBits();
1025 VA.getValVT(), ArgValue,
1093 CCValAssign &VA = RVLocs[i];
1094 assert(VA.isRegLoc() && "Only register-returns should be created by PCS");
1104 switch (VA.getLocInfo()) {
1112 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1115 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1119 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1121 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1214 CCValAssign &VA = ArgLocs[i];
1222 switch (VA.getLocInfo()) {
1228 unsigned SrcSize = VA.getValVT().getSizeInBits();
1240 VA.getLocVT(),
1241 DAG.getUNDEF(VA.getLocVT()),
1249 VA.getLocVT(), Arg);
1253 if (VA.isRegLoc()) {
1257 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1261 assert(VA.isMemLoc() && "unexpected argument location");
1267 VA.getLocVT().getSizeInBits();
1269 int32_t Offset = VA.getLocMemOffset() + FPDiff;
1279 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset());
1282 DstInfo = MachinePointerInfo::getStack(VA.getLocMemOffset());
1411 CCValAssign VA = RVLocs[i];
1415 assert(VA.isRegLoc() && "Memory locations not expected for call return");
1417 SDValue Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1422 switch (VA.getLocInfo()) {
1426 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1433 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
