Lines Matching refs:AArch64
1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
14 #include "AArch64.h"
38 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
47 if (DestReg == AArch64::XSP || SrcReg == AArch64::XSP) {
49 BuildMI(MBB, I, DL, get(AArch64::ADDxxi_lsl0_s), DestReg)
53 } else if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
55 BuildMI(MBB, I, DL, get(AArch64::ADDwwi_lsl0_s), DestReg)
59 } else if (DestReg == AArch64::NZCV) {
60 assert(AArch64::GPR64RegClass.contains(SrcReg));
62 BuildMI(MBB, I, DL, get(AArch64::MSRix))
65 } else if (SrcReg == AArch64::NZCV) {
66 assert(AArch64::GPR64RegClass.contains(DestReg));
68 BuildMI(MBB, I, DL, get(AArch64::MRSxi), DestReg)
70 } else if (AArch64::GPR64RegClass.contains(DestReg)) {
71 assert(AArch64::GPR64RegClass.contains(SrcReg));
72 Opc = AArch64::ORRxxx_lsl;
73 ZeroReg = AArch64::XZR;
74 } else if (AArch64::GPR32RegClass.contains(DestReg)) {
75 assert(AArch64::GPR32RegClass.contains(SrcReg));
76 Opc = AArch64::ORRwww_lsl;
77 ZeroReg = AArch64::WZR;
78 } else if (AArch64::FPR32RegClass.contains(DestReg)) {
79 assert(AArch64::FPR32RegClass.contains(SrcReg));
80 BuildMI(MBB, I, DL, get(AArch64::FMOVss), DestReg)
83 } else if (AArch64::FPR64RegClass.contains(DestReg)) {
84 assert(AArch64::FPR64RegClass.contains(SrcReg));
85 BuildMI(MBB, I, DL, get(AArch64::FMOVdd), DestReg)
88 } else if (AArch64::FPR128RegClass.contains(DestReg)) {
89 assert(AArch64::FPR128RegClass.contains(SrcReg));
98 BuildMI(MBB, I, DL, get(AArch64::LSFP128_PreInd_STR), AArch64::XSP)
100 .addReg(AArch64::XSP)
103 BuildMI(MBB, I, DL, get(AArch64::LSFP128_PostInd_LDR), DestReg)
104 .addReg(AArch64::XSP, RegState::Define)
105 .addReg(AArch64::XSP)
122 return Opc == AArch64::Bcc || Opc == AArch64::CBZw || Opc == AArch64::CBZx ||
123 Opc == AArch64::CBNZw || Opc == AArch64::CBNZx ||
124 Opc == AArch64::TBZwii || Opc == AArch64::TBZxii ||
125 Opc == AArch64::TBNZwii || Opc == AArch64::TBNZxii;
136 case AArch64::Bcc:
137 case AArch64::CBZw:
138 case AArch64::CBZx:
139 case AArch64::CBNZw:
140 case AArch64::CBNZx:
147 case AArch64::TBZwii:
148 case AArch64::TBZxii:
149 case AArch64::TBNZwii:
150 case AArch64::TBNZxii:
187 if (LastOpc == AArch64::Bimm) {
204 if (AllowModify && LastOpc == AArch64::Bimm) {
205 while (SecondLastOpc == AArch64::Bimm) {
225 if (LastOpc == AArch64::Bimm) {
226 if (SecondLastOpc == AArch64::Bcc) {
228 Cond.push_back(MachineOperand::CreateImm(AArch64::Bcc));
241 if (SecondLastOpc == AArch64::Bimm && LastOpc == AArch64::Bimm) {
256 case AArch64::Bcc: {
262 case AArch64::CBZw:
263 Cond[0].setImm(AArch64::CBNZw);
265 case AArch64::CBZx:
266 Cond[0].setImm(AArch64::CBNZx);
268 case AArch64::CBNZw:
269 Cond[0].setImm(AArch64::CBZw);
271 case AArch64::CBNZx:
272 Cond[0].setImm(AArch64::CBZx);
274 case AArch64::TBZwii:
275 Cond[0].setImm(AArch64::TBNZwii);
277 case AArch64::TBZxii:
278 Cond[0].setImm(AArch64::TBNZxii);
280 case AArch64::TBNZwii:
281 Cond[0].setImm(AArch64::TBZwii);
283 case AArch64::TBNZxii:
284 Cond[0].setImm(AArch64::TBZxii);
298 BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(TBB);
313 BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(FBB);
326 if (I->getOpcode() != AArch64::Bimm && !isCondBranch(I->getOpcode()))
351 case AArch64::TLSDESC_BLRx: {
353 BuildMI(MBB, MBBI, MI.getDebugLoc(), get(AArch64::TLSDESCCALL))
355 MI.setDesc(get(AArch64::BLRx));
388 case 4: StoreOp = AArch64::LS32_STR; break;
389 case 8: StoreOp = AArch64::LS64_STR; break;
398 case 4: StoreOp = AArch64::LSFP32_STR; break;
399 case 8: StoreOp = AArch64::LSFP64_STR; break;
400 case 16: StoreOp = AArch64::LSFP128_STR; break;
434 case 4: LoadOp = AArch64::LS32_LDR; break;
435 case 8: LoadOp = AArch64::LS64_LDR; break;
444 case 4: LoadOp = AArch64::LSFP32_LDR; break;
445 case 8: LoadOp = AArch64::LSFP64_LDR; break;
446 case 16: LoadOp = AArch64::LSFP128_LDR; break;
468 if (I->getOpcode() == AArch64::ADDxxi_lsl0_s) {
494 case AArch64::LS8_LDR: case AArch64::LS8_STR:
495 case AArch64::LSFP8_LDR: case AArch64::LSFP8_STR:
496 case AArch64::LDRSBw:
497 case AArch64::LDRSBx:
502 case AArch64::LS16_LDR: case AArch64::LS16_STR:
503 case AArch64::LSFP16_LDR: case AArch64::LSFP16_STR:
504 case AArch64::LDRSHw:
505 case AArch64::LDRSHx:
510 case AArch64::LS32_LDR: case AArch64::LS32_STR:
511 case AArch64::LSFP32_LDR: case AArch64::LSFP32_STR:
512 case AArch64::LDRSWx:
513 case AArch64::LDPSWx:
518 case AArch64::LS64_LDR: case AArch64::LS64_STR:
519 case AArch64::LSFP64_LDR: case AArch64::LSFP64_STR:
520 case AArch64::PRFM:
525 case AArch64::LSFP128_LDR: case AArch64::LSFP128_STR:
530 case AArch64::LSPair32_LDR: case AArch64::LSPair32_STR:
531 case AArch64::LSFPPair32_LDR: case AArch64::LSFPPair32_STR:
536 case AArch64::LSPair64_LDR: case AArch64::LSPair64_STR:
537 case AArch64::LSFPPair64_LDR: case AArch64::LSFPPair64_STR:
542 case AArch64::LSFPPair128_LDR: case AArch64::LSFPPair128_STR:
559 if (MI.getOpcode() == AArch64::INLINEASM)
574 case AArch64::TLSDESCCALL:
615 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVZxii), ScratchReg)
621 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
629 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
637 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
644 unsigned AddOp = NumBytes > 0 ? AArch64::ADDxxx_uxtx : AArch64::SUBxxx_uxtx;
660 LowOp = AArch64::ADDxxi_lsl0_s;
661 HighOp = AArch64::ADDxxi_lsl12_s;
663 LowOp = AArch64::SUBxxi_lsl0_s;
664 HighOp = AArch64::SUBxxi_lsl12_s;
692 emitRegUpdate(MBB, MI, dl, TII, AArch64::XSP, AArch64::XSP, AArch64::X16,
727 case AArch64::TLSDESC_BLRx:
766 AArch64::X0)
785 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
792 .addReg(AArch64::X0);
