Lines Matching defs:Lane
73 unsigned Reg, unsigned Lane,
79 unsigned DReg, unsigned Lane,
94 DebugLoc DL, unsigned DReg, unsigned Lane,
434 unsigned Reg, unsigned Lane, bool QPR) {
443 .addImm(Lane));
448 // Creates a SPR register from a DPR by copying the value in lane 0.
453 unsigned DReg, unsigned Lane,
460 .addReg(DReg, 0, Lane);
504 DebugLoc DL, unsigned DReg, unsigned Lane,
513 .addImm(Lane);
567 unsigned Lane;
569 case ARM::ssub_0: Lane = 0; break;
570 case ARM::ssub_1: Lane = 1; break;
571 default: llvm_unreachable("Unknown preferred lane!");
578 Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
603 // lane, and the other lane(s) of the DPR/QPR register
