Lines Matching refs:Out
12 // out-of-order with appropriate forwarding. The ARM architecture allows VFP
183 // MI is known to be dead. Figure out what instructions
279 // Find the thing we're subreg copying out of - is it of the same
435 unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass :
441 Out)
445 return Out;
455 unsigned Out = MRI->createVirtualRegister(TRC);
459 TII->get(TargetOpcode::COPY), Out)
462 return Out;
471 unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
475 Out)
480 return Out;
490 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
494 TII->get(ARM::VEXTd32), Out)
498 return Out;
506 unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
510 TII->get(TargetOpcode::INSERT_SUBREG), Out)
515 return Out;
522 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
526 TII->get(TargetOpcode::IMPLICIT_DEF), Out);
527 return Out;
539 unsigned Out;
549 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
555 Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
560 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
576 Out = createImplicitDef(MBB, InsertPt, DL);
577 Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
578 Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
581 return Out;
642 // Now, work out if the instruction causes a SPR->DPR dependency.
