Lines Matching defs:Class
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
784 llvm_unreachable("Unknown reg class!");
809 llvm_unreachable("Unknown reg class!");
826 llvm_unreachable("Unknown reg class!");
846 llvm_unreachable("Unknown reg class!");
868 llvm_unreachable("Unknown reg class!");
885 llvm_unreachable("Unknown reg class!");
888 class!");
974 llvm_unreachable("Unknown reg class!");
1002 llvm_unreachable("Unknown reg class!");
1016 llvm_unreachable("Unknown reg class!");
1036 llvm_unreachable("Unknown reg class!");
1057 llvm_unreachable("Unknown reg class!");
1076 llvm_unreachable("Unknown reg class!");
2650 unsigned Class = Desc.getSchedClass();
2651 int ItinUOps = ItinData->getNumMicroOps(Class);
3616 unsigned Class = MCID.getSchedClass();
3619 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3623 unsigned Latency = ItinData->getStageLatency(Class);
