Lines Matching full:opcode
59 uint16_t MLxOpc; // MLA / MLS opcode
60 uint16_t MulOpc; // Expanded multiplication opcode
61 uint16_t AddSubOpc; // Expanded add / sub opcode
1181 // Change the opcode and operands.
1255 unsigned Opcode = Orig->getOpcode();
1256 switch (Opcode) {
1268 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1296 int Opcode = MI0->getOpcode();
1297 if (Opcode == ARM::t2LDRpci ||
1298 Opcode == ARM::t2LDRpci_pic ||
1299 Opcode == ARM::tLDRpci ||
1300 Opcode == ARM::tLDRpci_pic ||
1301 Opcode == ARM::MOV_ga_dyn ||
1302 Opcode == ARM::MOV_ga_pcrel ||
1303 Opcode == ARM::MOV_ga_pcrel_ldr ||
1304 Opcode == ARM::t2MOV_ga_dyn ||
1305 Opcode == ARM::t2MOV_ga_pcrel) {
1306 if (MI1->getOpcode() != Opcode)
1316 if (Opcode == ARM::MOV_ga_dyn ||
1317 Opcode == ARM::MOV_ga_pcrel ||
1318 Opcode == ARM::MOV_ga_pcrel_ldr ||
1319 Opcode == ARM::t2MOV_ga_dyn ||
1320 Opcode == ARM::t2MOV_ga_pcrel)
1342 } else if (Opcode == ARM::PICLDR) {
1343 if (MI1->getOpcode() != Opcode)
1599 llvm_unreachable("Unknown unconditional branch opcode!");
1810 unsigned Opcode = MI.getOpcode();
1816 if (Opcode == ARM::INLINEASM)
1819 if (Opcode == ARM::ADDri) {
1907 // Attempt to fold address comp. if opcode has offset bits
2617 // the target to provide this information based on the instruction opcode and
3098 /// itinerary based on the def opcode and alignment. The caller will ensure that
3362 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3380 if (isZeroCost(DefMCID.Opcode))
3625 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3643 unsigned Opcode = Node->getMachineOpcode();
3644 switch (Opcode) {
3646 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3700 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
3703 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
3832 llvm_unreachable("cannot handle opcode!");
