Lines Matching refs:DefMI
1690 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1691 bool Invert = !DefMI;
1692 if (!DefMI)
1693 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1694 if (!DefMI)
1697 // Create a new predicated version of DefMI.
1700 DefMI->getDesc(),
1703 // Copy all the DefMI operands, excluding its (null) predicate.
1704 const MCInstrDesc &DefDesc = DefMI->getDesc();
1707 NewMI.addOperand(DefMI->getOperand(i));
1716 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1729 // The caller will erase MI, but not DefMI.
1730 DefMI->eraseFromParent();
2274 MachineInstr *DefMI, unsigned Reg,
2277 unsigned DefOpc = DefMI->getOpcode();
2280 if (!DefMI->getOperand(1).isImm())
2287 const MCInstrDesc &DefMCID = DefMI->getDesc();
2290 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2292 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2293 // to delete DefMI.
2308 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2385 DefMI->eraseFromParent();
3101 const MachineInstr *DefMI,
3111 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3123 unsigned ShAmt = DefMI->getOperand(3).getImm();
3136 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3154 unsigned ShAmt = DefMI->getOperand(3).getImm();
3282 const MachineInstr *DefMI, unsigned DefIdx,
3289 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3291 const MCInstrDesc *DefMCID = &DefMI->getDesc();
3295 if (DefMI->isBundle()) {
3296 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3297 DefMCID = &DefMI->getDesc();
3299 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3300 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3318 if (DefMI->getOpcode() == ARM::FMSTAT) {
3328 unsigned Latency = getInstrLatency(ItinData, DefMI);
3335 const MachineFunction *MF = DefMI->getParent()->getParent();
3347 unsigned DefAlign = DefMI->hasOneMemOperand()
3348 DefMI->memoperands_begin())->getAlignment() : 0;
3363 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3656 const MachineInstr *DefMI, unsigned DefIdx,
3658 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3666 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
3668 Latency = getInstrLatency(ItinData, DefMI);
3677 const MachineInstr *DefMI, unsigned DefIdx) const {
3681 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3683 unsigned DefClass = DefMI->getDesc().getSchedClass();
