Lines Matching refs:MIB
672 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
673 MIB.addReg(SrcReg, getKillRegState(KillSrc));
675 MIB.addReg(SrcReg, getKillRegState(KillSrc));
676 AddDefaultPred(MIB);
745 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
749 return MIB.addReg(Reg, State);
752 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
753 return MIB.addReg(Reg, State, SubIdx);
793 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
794 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
795 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
796 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
798 AddDefaultPred(MIB);
802 MachineInstrBuilder MIB =
805 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
806 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
837 MachineInstrBuilder MIB =
841 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
842 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
843 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
858 MachineInstrBuilder MIB =
862 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
863 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
864 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
865 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
872 MachineInstrBuilder MIB =
876 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
877 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
878 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
879 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
880 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
881 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
882 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
883 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
981 MachineInstrBuilder MIB;
984 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
985 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
986 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
987 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
989 AddDefaultPred(MIB);
993 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
995 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
996 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1000 MIB.addReg(DestReg, RegState::ImplicitDefine);
1025 MachineInstrBuilder MIB =
1029 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1030 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1031 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1033 MIB.addReg(DestReg, RegState::ImplicitDefine);
1045 MachineInstrBuilder MIB =
1049 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1050 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1051 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1052 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1054 MIB.addReg(DestReg, RegState::ImplicitDefine);
1061 MachineInstrBuilder MIB =
1065 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1066 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1067 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1068 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1069 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1070 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1071 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1072 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1074 MIB.addReg(DestReg, RegState::ImplicitDefine);
1173 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1185 AddDefaultPred(MIB);
1192 MIB.addReg(SrcRegS, RegState::Implicit);
1268 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1271 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
3828 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
3850 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
3872 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
3878 MIB.addReg(SrcReg, RegState::Implicit);
3901 MIB.addReg(DReg, RegState::Define)
3905 AddDefaultPred(MIB);
3909 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
3911 MIB.addReg(ImplicitSReg, RegState::Implicit);
3937 MIB.addReg(DDst, RegState::Define)
3940 AddDefaultPred(MIB);
3944 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
3945 MIB.addReg(SrcReg, RegState::Implicit);
3947 MIB.addReg(ImplicitSReg, RegState::Implicit);
3985 MIB.addReg(DDst, RegState::Define);
3991 MIB.addReg(CurReg, getUndefRegState(CurUndef));
3995 MIB.addReg(CurReg, getUndefRegState(CurUndef));
3997 MIB.addImm(1);
3998 AddDefaultPred(MIB);
4001 MIB.addReg(SrcReg, RegState::Implicit);
4005 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4007 MIB.addReg(ImplicitSReg, RegState::Implicit);
