Lines Matching refs:SrcReg
645 unsigned DestReg, unsigned SrcReg,
648 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
652 .addReg(SrcReg, getKillRegState(KillSrc))));
657 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
666 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
668 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
673 MIB.addReg(SrcReg, getKillRegState(KillSrc));
675 MIB.addReg(SrcReg, getKillRegState(KillSrc));
686 if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
688 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
691 else if (ARM::DPairRegClass.contains(DestReg, SrcReg))
693 else if (ARM::DTripleRegClass.contains(DestReg, SrcReg))
695 else if (ARM::DQuadRegClass.contains(DestReg, SrcReg))
697 else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg))
700 else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg))
702 else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg))
704 else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg))
712 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
713 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
722 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing);
741 Mov->addRegisterKilled(SrcReg, TRI);
758 unsigned SrcReg, bool isKill, int FI,
777 .addReg(SrcReg, getKillRegState(isKill))
781 .addReg(SrcReg, getKillRegState(isKill))
789 .addReg(SrcReg, getKillRegState(isKill))
794 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
795 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
805 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
806 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
817 .addReg(SrcReg, getKillRegState(isKill))
821 .addReg(SrcReg, getKillRegState(isKill))
834 .addReg(SrcReg, getKillRegState(isKill))
841 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
842 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
843 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
855 .addReg(SrcReg, getKillRegState(isKill))
862 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
863 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
864 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
865 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
876 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
877 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
878 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
879 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
880 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
881 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
882 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
883 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
1948 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1952 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
1958 SrcReg = MI->getOperand(0).getReg();
1965 SrcReg = MI->getOperand(0).getReg();
1972 SrcReg = MI->getOperand(0).getReg();
1986 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1993 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2035 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2042 ((OI->getOperand(1).getReg() == SrcReg &&
2045 OI->getOperand(2).getReg() == SrcReg)))
2052 OI->getOperand(1).getReg() == SrcReg &&
2066 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2069 // Get the unique definition of SrcReg.
2070 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2075 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2077 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
2081 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2131 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2225 Sub->getOperand(2).getReg() == SrcReg)
3826 unsigned DstReg, SrcReg, DReg;
3843 SrcReg = MI->getOperand(1).getReg();
3851 .addReg(SrcReg)
3852 .addReg(SrcReg));
3861 SrcReg = MI->getOperand(1).getReg();
3866 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
3878 MIB.addReg(SrcReg, RegState::Implicit);
3887 SrcReg = MI->getOperand(1).getReg();
3903 .addReg(SrcReg)
3920 SrcReg = MI->getOperand(1).getReg();
3924 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
3945 MIB.addReg(SrcReg, RegState::Implicit);
3982 NewMIB.addReg(SrcReg, RegState::Implicit);
4001 MIB.addReg(SrcReg, RegState::Implicit);
