Cross Reference: /external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines Matching refs:desc

46                cl::desc("Enable ARM 2-addr to 3-addr conv"));
50            cl::desc("Widen ARM vmovs to vmovd when possible"));
55      cl::desc("Clearance before partial register updates"));
1811   const MCInstrDesc &Desc = MI.getDesc();
1812   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2393     const MCInstrDesc &Desc = MI->getDesc();
2394     int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2649   const MCInstrDesc &Desc = MI->getDesc();
2650   unsigned Class = Desc.getSchedClass();
2653     if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
2689     unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2725     unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;

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