Lines Matching defs:Lane
89 // For quad-register load-lane and store-lane pseudo instructors, the
91 // OddDblSpc depending on the lane number operand.
108 uint8_t RegElts; // elements per D register; used for lane ops
503 // The lane operand is always the 3rd from last operand, before the 2
505 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
507 // Adjust the lane and spacing as needed for Q registers.
508 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
509 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
511 Lane -= RegElts;
513 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
557 // Add the lane number operand.
558 MIB.addImm(Lane);
1010 unsigned Lane = TRI->getEncodingValue(SrcReg) & 1;
1012 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0,
1014 // The lane is [0,1] for the containing DReg superregister.
1019 // Add the lane select operand.
1020 MIB.addImm(Lane);
