Lines Matching refs:getDeadRegState
391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
522 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
524 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
526 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
528 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
570 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
628 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
658 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
874 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
922 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
961 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
962 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
965 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));