Lines Matching full:instruction
145 virtual bool TargetSelectInstruction(const Instruction *I);
154 // Instruction selection routines.
156 bool SelectLoad(const Instruction *I);
157 bool SelectStore(const Instruction *I);
158 bool SelectBranch(const Instruction *I);
159 bool SelectIndirectBr(const Instruction *I);
160 bool SelectCmp(const Instruction *I);
161 bool SelectFPExt(const Instruction *I);
162 bool SelectFPTrunc(const Instruction *I);
163 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
164 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
165 bool SelectIToFP(const Instruction *I, bool isSigned);
166 bool SelectFPToI(const Instruction *I, bool isSigned);
167 bool SelectDiv(const Instruction *I, bool isSigned);
168 bool SelectRem(const Instruction *I, bool isSigned);
169 bool SelectCall(const Instruction *I, const char *IntrMemName);
171 bool SelectSelect(const Instruction *I);
172 bool SelectRet(const Instruction *I);
173 bool SelectTrunc(const Instruction *I);
174 bool SelectIntExt(const Instruction *I);
175 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
217 const Instruction *I, CallingConv::ID CC,
219 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
564 // If we can do this in a single instruction without a constant pool entry
800 unsigned Opcode = Instruction::UserOp1;
801 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
816 // Fast instruction selection doesn't support the special
823 case Instruction::BitCast:
826 case Instruction::IntToPtr:
831 case Instruction::PtrToInt:
836 case Instruction::GetElementPtr: {
859 (!isa<Instruction>(Op) ||
860 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
888 case Instruction::Alloca: {
950 // Since the offset is too large for the load/store instruction
1089 // Create the base instruction, then add the operands.
1109 bool ARMFastISel::SelectLoad(const Instruction *I) {
1212 // Create the base instruction, then add the operands.
1220 bool ARMFastISel::SelectStore(const Instruction *I) {
1294 bool ARMFastISel::SelectBranch(const Instruction *I) {
1390 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1520 bool ARMFastISel::SelectCmp(const Instruction *I) {
1551 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1570 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1589 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1634 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1667 bool ARMFastISel::SelectSelect(const Instruction *I) {
1728 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1756 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1778 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1804 // in the instruction, rather then materializing the value in a register.
1816 Instruction *I, unsigned ISDOpcode) {
2045 const Instruction *I, CallingConv::ID CC,
2099 bool ARMFastISel::SelectRet(const Instruction *I) {
2167 // Add register to return instruction.
2200 // vector of passed arguments for the Instruction in I. We can assume that we
2206 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2297 bool ARMFastISel::SelectCall(const Instruction *I,
2585 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2615 // Table of which combinations can be emitted as a single instruction,
2636 // Table governing the instruction(s) to be emitted.
2661 { // Single instruction.
2711 // instruction sequences: both are shifts.
2737 // Second instruction consumes the first's result.
2744 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2769 bool ARMFastISel::SelectShift(const Instruction *I,
2825 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2828 case Instruction::Load:
2830 case Instruction::Store:
2832 case Instruction::Br:
2834 case Instruction::IndirectBr:
2836 case Instruction::ICmp:
2837 case Instruction::FCmp:
2839 case Instruction::FPExt:
2841 case Instruction::FPTrunc:
2843 case Instruction::SIToFP:
2845 case Instruction::UIToFP:
2847 case Instruction::FPToSI:
2849 case Instruction::FPToUI:
2851 case Instruction::Add:
2853 case Instruction::Or:
2855 case Instruction::Sub:
2857 case Instruction::FAdd:
2859 case Instruction::FSub:
2861 case Instruction::FMul:
2863 case Instruction::SDiv:
2865 case Instruction::UDiv:
2867 case Instruction::SRem:
2869 case Instruction::URem:
2871 case Instruction::Call:
2875 case Instruction::Select:
2877 case Instruction::Ret:
2879 case Instruction::Trunc:
2881 case Instruction::ZExt:
2882 case Instruction::SExt:
2884 case Instruction::Shl:
2886 case Instruction::LShr:
2888 case Instruction::AShr:
2915 /// vreg is being provided by the specified load instruction. If possible,
2916 /// try to fold the load as an operand to the instruction, returning true if
3060 // use is a bitcast (which isn't turned into an instruction).
