Lines Matching refs:ISD
210 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
953 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
1789 case ISD::ADD:
1792 case ISD::OR:
1795 case ISD::SUB:
1834 case ISD::FADD:
1837 case ISD::FSUB:
1840 case ISD::FMUL:
1906 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1996 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
2111 SmallVector<ISD::OutputArg, 4> Outs;
2230 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2244 ISD::ArgFlagsTy Flags;
2341 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2354 ISD::ArgFlagsTy Flags;
2852 return SelectBinaryIntOp(I, ISD::ADD);
2854 return SelectBinaryIntOp(I, ISD::OR);
2856 return SelectBinaryIntOp(I, ISD::SUB);
2858 return SelectBinaryFPOp(I, ISD::FADD);
2860 return SelectBinaryFPOp(I, ISD::FSUB);
2862 return SelectBinaryFPOp(I, ISD::FMUL);
