Lines Matching refs:ResultReg
183 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
296 unsigned ResultReg = createResultReg(RC);
299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
300 return ResultReg;
306 unsigned ResultReg = createResultReg(RC);
310 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
316 TII.get(TargetOpcode::COPY), ResultReg)
319 return ResultReg;
326 unsigned ResultReg = createResultReg(RC);
330 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
338 TII.get(TargetOpcode::COPY), ResultReg)
341 return ResultReg;
349 unsigned ResultReg = createResultReg(RC);
353 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
363 TII.get(TargetOpcode::COPY), ResultReg)
366 return ResultReg;
373 unsigned ResultReg = createResultReg(RC);
377 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
385 TII.get(TargetOpcode::COPY), ResultReg)
388 return ResultReg;
395 unsigned ResultReg = createResultReg(RC);
399 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
407 TII.get(TargetOpcode::COPY), ResultReg)
410 return ResultReg;
418 unsigned ResultReg = createResultReg(RC);
422 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
432 TII.get(TargetOpcode::COPY), ResultReg)
435 return ResultReg;
441 unsigned ResultReg = createResultReg(RC);
445 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
451 TII.get(TargetOpcode::COPY), ResultReg)
454 return ResultReg;
460 unsigned ResultReg = createResultReg(RC);
464 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
471 ResultReg)
474 return ResultReg;
480 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
485 DL, TII.get(TargetOpcode::COPY), ResultReg)
487 return ResultReg;
761 unsigned ResultReg = createResultReg(RC);
764 TII.get(Opc), ResultReg)
767 return ResultReg;
940 unsigned ResultReg = createResultReg(RC);
943 TII.get(Opc), ResultReg)
946 Addr.Base.Reg = ResultReg;
1007 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
1091 ResultReg = createResultReg(RC);
1092 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1094 TII.get(Opc), ResultReg);
1103 .addReg(ResultReg));
1104 ResultReg = MoveReg;
1123 unsigned ResultReg;
1124 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1126 UpdateValueMap(I, ResultReg);
1626 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1628 ResultReg)
1630 UpdateValueMap(I, ResultReg);
1653 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1655 ResultReg)
1660 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1717 unsigned ResultReg = createResultReg(RC);
1719 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1722 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1724 UpdateValueMap(I, ResultReg);
1808 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1810 TII.get(Opc), ResultReg)
1812 UpdateValueMap(I, ResultReg);
1850 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1852 TII.get(Opc), ResultReg)
1854 UpdateValueMap(I, ResultReg);
2065 unsigned ResultReg = createResultReg(DstRC);
2067 TII.get(ARM::VMOVDRR), ResultReg)
2075 UpdateValueMap(I, ResultReg);
2086 unsigned ResultReg = createResultReg(DstRC);
2088 ResultReg).addReg(RVLocs[0].getLocReg());
2092 UpdateValueMap(I, ResultReg);
2473 unsigned ResultReg;
2474 RV = ARMEmitLoad(VT, ResultReg, Src);
2476 RV = ARMEmitStore(VT, ResultReg, Dest);
2708 unsigned ResultReg;
2724 ResultReg = createResultReg(RC);
2731 *FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opcode), ResultReg);
2738 SrcReg = ResultReg;
2741 return ResultReg;
2763 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2764 if (ResultReg == 0) return false;
2765 UpdateValueMap(I, ResultReg);
2805 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2806 if(ResultReg == 0) return false;
2809 TII.get(Opc), ResultReg)
2820 UpdateValueMap(I, ResultReg);
2950 unsigned ResultReg = MI->getOperand(0).getReg();
2951 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
3061 unsigned ResultReg = createResultReg(RC);
3063 ResultReg).addReg(DstReg, getKillRegState(true));
3064 UpdateValueMap(I, ResultReg);
