Lines Matching refs:RetVT
139 unsigned FastEmitInst_extractsubreg(MVT RetVT,
216 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
477 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
480 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
2044 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2054 if (RetVT != MVT::isVoid) {
2057 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2060 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2081 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2211 MVT RetVT;
2213 RetVT = MVT::isVoid;
2214 else if (!isTypeLegal(RetTy, RetVT))
2218 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2221 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2222 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2289 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2320 MVT RetVT;
2322 RetVT = MVT::isVoid;
2323 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2324 RetVT != MVT::i8 && RetVT != MVT::i1)
2328 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2329 RetVT != MVT::i16 && RetVT != MVT::i32) {
2332 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2333 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2433 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
