Lines Matching refs:no_shift
2653 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2654 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2655 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2656 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2657 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2658 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2663 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2664 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2665 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2666 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2667 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2668 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2671 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2672 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2673 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2674 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2675 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2676 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2701 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2712 bool ImmIsSO = (Shift != ARM_AM::no_shift);
