Lines Matching defs:Srl
346 // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
350 // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
352 // operand of 'add' and the 'and' and 'srl' would become a bits extraction
382 // Look for (and (srl X, c1), c2).
383 SDValue Srl = N1.getOperand(0);
385 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
404 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
405 Srl.getOperand(0),
408 Srl, CurDAG->getConstant(And_imm, MVT::i32));
2261 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2282 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL);
2678 case ISD::SRL:
