Lines Matching refs:ISD
291 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
343 if (N->getOpcode() != ISD::ADD)
358 if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
359 if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
385 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
404 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
407 N1 = CurDAG->getNode(ISD
409 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
433 if (Use->getOpcode() == ISD::CopyToReg)
533 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
535 if (N.getOpcode() == ISD::FrameIndex) {
546 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
556 if (N.getOpcode() == ISD::SUB)
561 if (Base.getOpcode() == ISD::FrameIndex) {
581 if (N.getOpcode() == ISD::MUL &&
605 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
606 // ISD::OR that is equivalent to an ISD::ADD.
611 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
619 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
645 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
680 if (N.getOpcode() == ISD::MUL &&
704 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
705 // ISD::OR that is equivalent to an ADD.
708 if (N.getOpcode() == ISD::FrameIndex) {
714 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
725 if (N.getOpcode() != ISD::SUB) {
730 if (Base.getOpcode() == ISD::FrameIndex) {
760 ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
786 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
817 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
820 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
853 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
856 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
873 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
876 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
898 if (N.getOpcode() == ISD::SUB) {
908 if (N.getOpcode() == ISD::FrameIndex) {
923 if (Base.getOpcode() == ISD::FrameIndex) {
948 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
951 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
969 if (N.getOpcode() == ISD::FrameIndex) {
975 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
988 if (Base.getOpcode() == ISD::FrameIndex) {
1036 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
1037 if (AM != ISD::POST_INC)
1067 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
1090 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1146 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1153 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1213 if (N.getOpcode() == ISD::FrameIndex) {
1225 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1231 if (Base.getOpcode() == ISD::FrameIndex) {
1277 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1279 if (N.getOpcode() == ISD::FrameIndex) {
1290 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1292 if (Base.getOpcode() == ISD::TargetConstantPool)
1306 if (N.getOpcode() == ISD::SUB)
1311 if (Base.getOpcode() == ISD::FrameIndex) {
1330 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1336 if (N.getOpcode() == ISD::SUB)
1341 if (Base.getOpcode() == ISD::FrameIndex) {
1357 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1362 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1375 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1428 if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N))
1440 if (Base.getOpcode() == ISD::FrameIndex) {
1458 ISD::MemIndexedMode AM = LD->getAddressingMode();
1459 if (AM == ISD::UNINDEXED)
1464 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1483 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1487 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1531 ISD::MemIndexedMode AM = LD->getAddressingMode();
1532 if (AM == ISD::UNINDEXED)
1536 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1538 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
2253 if (N->getOpcode() == ISD::AND) {
2254 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2261 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2282 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL);
2303 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2441 assert(CC.getOpcode() == ISD::Constant);
2442 assert(CCR.getOpcode() == ISD::Register);
2522 /// Target-specific DAG combining for ISD::XOR.
2540 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
2597 case ISD::INLINEASM: {
2603 case ISD::XOR: {
2611 case ISD::Constant: {
2660 case ISD::FrameIndex: {
2678 case ISD::SRL:
2682 case ISD::SRA:
2686 case ISD::MUL:
2726 case ISD::AND: {
2748 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2771 case ISD::UMUL_LOHI: {
2787 case ISD::SMUL_LOHI: {
2835 case ISD::LOAD: {
2866 assert(N1.getOpcode() == ISD::BasicBlock);
2867 assert(N2.getOpcode() == ISD::Constant);
2868 assert(N3.getOpcode() == ISD::Register);
3159 case ISD::INTRINSIC_VOID:
3160 case ISD::INTRINSIC_W_CHAIN: {
3406 case ISD::INTRINSIC_WO_CHAIN: {
3457 case ISD::CONCAT_VECTORS:
3633 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
