Lines Matching defs:N0
3830 /// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
3842 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
3843 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
3884 /// vrev: N0 = [k1 k0 k3 k2 ]
3902 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
3903 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
5482 SDNode *N0 = N->getOperand(0).getNode();
5484 return N0->hasOneUse() && N1->hasOneUse() &&
5485 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
5493 SDNode *N0 = N->getOperand(0).getNode();
5495 return N0->hasOneUse() && N1->hasOneUse() &&
5496 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
5507 SDNode *N0 = Op.getOperand(0).getNode();
5511 bool isN0SExt = isSignExtended(N0, DAG);
5516 bool isN0ZExt = isZeroExtended(N0, DAG);
5523 if (isN1SExt && isAddSubSExt(N0, DAG)) {
5526 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
5530 std::swap(N0, N1);
5551 Op0 = SkipExtensionForVMULL(N0, DAG);
5566 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
5567 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
5569 return DAG.getNode(N0->getOpcode(), DL, VT,
5606 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
5611 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
5613 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5629 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5630 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
5633 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5634 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5637 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5638 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5639 return N0;
5648 SDValue N0 = Op.getOperand(0);
5653 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
5656 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5660 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5665 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
5668 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5669 N0 = LowerCONCAT_VECTORS(N0, DAG);
5671 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
5672 return N0;
5674 return LowerSDIV_v4i16(N0, N1, dl, DAG);
5683 SDValue N0 = Op.getOperand(0);
5688 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
5691 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5695 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5700 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
5703 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5704 N0 = LowerCONCAT_VECTORS(N0, DAG);
5706 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
5708 N0);
5709 return N0;
5715 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
5717 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5738 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5739 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
5742 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5743 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5746 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5747 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5748 return N0;
7883 SDValue N0 = N->getOperand(0);
7885 if (N0.getNode()->hasOneUse()) {
7886 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
7891 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
7900 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
7907 || N0.getOpcode() != ISD::BUILD_VECTOR
7917 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
7923 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7925 SDValue Vec = N0->getOperand(0)->getOperand(0);
7932 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
7933 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
7936 SDValue ExtVec0 = N0->getOperand(i);
8139 /// operands N0 and N1. This is a helper for PerformADDCombine that is
8142 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
8147 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
8152 if (N0.getNode()->hasOneUse()) {
8153 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
8164 SDValue N0 = N->getOperand(0);
8168 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
8173 N0, DCI, Subtarget);
8180 SDValue N0 = N->getOperand(0);
8185 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
8207 SDValue N0 = N->getOperand(0);
8209 unsigned Opcode = N0.getOpcode();
8216 std::swap(N0, N1);
8221 SDValue N00 = N0->getOperand(0);
8222 SDValue N01 = N0->getOperand(1);
8398 SDValue N0 = N->getOperand(0);
8399 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
8411 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
8427 N0->getOperand(1),
8428 N0->getOperand(0),
8457 SDValue N00 = N0.getOperand(0);
8462 SDValue MaskOp = N0.getOperand(1);
9304 SDValue N0 = Op->getOperand(0);
9326 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
9609 SDValue N0 = N->getOperand(0);
9610 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
9611 DAG.MaskedValueIsZero(N0.getOperand(0),
9613 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
9650 SDValue N0 = N->getOperand(0);
9656 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9657 SDValue Vec = N0.getOperand(0);
9658 SDValue Lane = N0.getOperand(1);
9660 EVT EltVT = N0.getValueType();
