Lines Matching refs:AddDefaultPred
6051 AddDefaultPred(MIB);
6052 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6067 AddDefaultPred(MIB);
6068 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6157 AddDefaultPred(MIB);
6161 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
6164 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
6171 AddDefaultPred(MIB);
6172 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6270 AddDefaultPred(MIB);
6275 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval)
6281 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6289 AddDefaultPred(MIB);
6290 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6376 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2LDREXD))
6382 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::LDREXD))
6395 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr :
6412 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), tmpRegLo)
6416 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), tmpRegHi)
6440 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2STREXD), storesuccess)
6458 AddDefaultPred
6462 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6522 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6528 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6535 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6549 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6558 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6562 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6567 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
6570 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6581 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
6586 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6589 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6709 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6715 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6720 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
6726 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
6731 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
6742 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
6748 AddDefaultPred(
6761 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
6767 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
6782 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
6785 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
6796 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
6802 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
6807 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
6817 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
6825 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
6837 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
6843 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
6848 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
6854 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
6859 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6874 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
6878 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6890 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
6894 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
6902 AddDefaultPred(
7085 AddDefaultPred(BuildMI(*BB, MI, dl,
7089 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
7092 AddDefaultPred(BuildMI(*BB, MI, dl,
7096 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
7100 AddDefaultPred(BuildMI(*BB, MI, dl,
7105 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
7123 AddDefaultPred(BuildMI(*BB, MI, dl,
7127 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
7131 AddDefaultPred(BuildMI(*BB, MI, dl,
7136 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
7184 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), VReg1)
7188 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
7202 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::LDRcp))
7236 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
7239 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
7242 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
7245 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
7249 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
7253 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
7261 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7287 AddDefaultPred(BuildMI(*BB, StartOfExit, dl,
7291 AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut)
7295 AddDefaultPred(BuildMI(*BB, StartOfExit, dl,
7299 AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut)
7564 AddDefaultPred(BuildMI(BB, dl,
7573 AddDefaultPred(BuildMI(BB, dl,
7589 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7651 AddDefaultPred(BuildMI(BB, dl,
